公开(公告)号：US20240095120A1

公开(公告)日：2024-03-21

申请号：US18169621

申请日：2023-02-15

Applicant: Micron Technology, Inc.

Inventor： Amitava Majumdar ,  Greg S. Hendrix ,  Anandhavel Nagendrakumar ,  Krunal Patel ,  Kirthi Shenoy ,  Danilo Caraccio ,  Ankush Lal ,  Frank F. Ross ,  Adam D. Gailey

IPC: G06F11/10

CPC classification number: G06F11/1048

Abstract: In a memory controller system, a system and method to identify memory errors which may require soft package repair or hard package repair to rows of DRAM memory. When data is written to a row of DRAM, the data is immediately and automatically read back and scanned for bit errors. If bit errors are identified, the data is corrected and written back to the same memory location. The memory location is re-read. If bit errors are again identified, the memory location is marked for soft or hard repair. If, upon rereading the memory location, additional bit errors are identified, a historical record of memory errors is reviewed to determine if bit errors have occurred previously at the same memory location. If yes, the memory location is again marked for a soft post package repair or a hard post package repair.

公开(公告)号：US20240087664A1

公开(公告)日：2024-03-14

申请号：US17943706

申请日：2022-09-13

Applicant: Micron Technology, Inc.

Inventor： William Yu ,  Daniele Balluchi ,  Chad B. Erickson ,  Danilo Caraccio

IPC: G11C29/38 ,  G11C29/10 ,  G11C29/12

CPC classification number: G11C29/38 ,  G11C29/10 ,  G11C29/1201

Abstract: Methods, systems, and devices related to built-in self-test burst patterns based on architecture of memory. A controller can be coupled to a memory device. The controller can include built-in self-test (BIST) circuitry. The BIST circuitry can include registers configured to store respective write burst patterns and read burst patterns based on an architecture of the memory device.

公开(公告)号：US20240061792A1

公开(公告)日：2024-02-22

申请号：US18235289

申请日：2023-08-17

Applicant: Micron Technology, Inc.

Inventor： Emanuele Confalonieri ,  Paolo Amato ,  Daniele Balluchi ,  Marco Sforzin ,  Danilo Caraccio ,  Niccolò Izzo ,  Graziano Mirichigni ,  Massimiliano Patriarca

IPC: G06F12/14 ,  G06F12/0804

CPC classification number: G06F12/1458 ,  G06F12/0804

Abstract: Systems, apparatuses, and methods related to data identity recognition for semiconductor devices are described. A system includes a host and a memory device coupled to the host via an interconnect bus. The host includes a host security manager configured to encrypt data of a command, perform a memory integrity check, allow access to memory of a memory device corresponding to an address of a command based on which entity associated with the host sent the command, generate security keys, program security keys into the memory device, program encryption ranges, or any combination thereof. The memory device includes a memory encryption manager and a memory device security manager. The memory device security manager is configured to detect whether a command was sent from a trusted domain of the host or non-trusted domain of the host and identify which entity associated with the host initiated the command.

公开(公告)号：US11880276B2

公开(公告)日：2024-01-23

申请号：US18099800

申请日：2023-01-20

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Daniele Balluchi

IPC: G11C29/00 ,  G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G06F12/02

CPC classification number: G06F11/1068 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/3037 ,  G06F12/0238 ,  G06F2212/7201

Abstract: Methods, systems, and devices for maintenance command interfaces for a memory system are described. A host system and a memory system may be configured according to a shared protocol that supports enhanced management of maintenance operations between the host system and memory system, such as maintenance operations to resolve error conditions at a physical address of a memory system. In some examples, a memory system may initiate maintenance operations based on detections performed at the memory system, and the memory system may provide a maintenance indication for the host system. In some examples, a host system may initiate maintenance operations based on detections performed at the host system. In various examples, the described maintenance signaling may include capability signaling between the host system and memory system, status indications between the host system and memory system, and other maintenance management techniques.

公开(公告)号：US20240004760A1

公开(公告)日：2024-01-04

申请号：US18216160

申请日：2023-06-29

Applicant: Micron Technology, Inc.

Inventor： Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio ,  Emanuele Confalonieri ,  Marco Sforzin

IPC: G06F11/10

CPC classification number: G06F11/1076

Abstract: A channel width can depend on a quantity of memory units (e.g., memory dice) that forms a channel as well as a size of the memory units. A memory system can operate with memory units configured to exchange (e.g., transfer to and/or from) data at a rate of smaller granularity that can provide more various options for channel widths, which can further allow a fine-tuned optimization of the memory system in association with its bandwidth and latency in transferring data from and/or to the memory units. The channels whose channel width is fine-tuned with such memory units can be further used to provide a reliability, availability, and serviceability (RAS) protection, such as a redundant array of independent disks (RAID) protection.

公开(公告)号：US20230395184A1

公开(公告)日：2023-12-07

申请号：US17959191

申请日：2022-10-03

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Antonino Caprì ,  Daniele Balluchi ,  Massimiliano Patriarca

IPC: G11C29/52 ,  G11C11/4093 ,  G11C11/406

CPC classification number: G11C29/52 ,  G11C11/4093 ,  G11C11/40615

Abstract: A soft post package repair (sPPR) request is detected. Data stored in a target row of a memory array associated with the sPPR request is written to a buffer. Execution of non-maintenance requests on the target row is suspended. Responsive to suspension of execution of non-maintenance requests on the target row, the sPPR request is executed on the target row. Subsequent to completion of the sPPR request, execution of non-maintenance requests on the target row is resumed and the data stored in the buffer is written to the repaired target row.

公开(公告)号：US11797717B2

公开(公告)日：2023-10-24

申请号：US16765224

申请日：2019-05-21

Applicant: Micron Technology, Inc.

Inventor： Paolo Amato ,  Marco Sforzin ,  Daniele Balluchi ,  Danilo Caraccio ,  Niccolo Izzo

IPC: G06F21/85 ,  G06F12/02 ,  G06F21/60 ,  G06F21/79 ,  G06F12/14

CPC classification number: G06F21/85 ,  G06F12/0246 ,  G06F12/1408 ,  G06F21/602 ,  G06F21/79

Abstract: The present disclosure relates to apparatuses and methods for memory management. The disclosure further relates to an interface protocol for flash memory devices including at least a memory array and a memory controller coupled to the memory array.
A host device is coupled to the memory device through a communication channel and a hardware and/or software full encryption-decryption scheme is adopted in the communication channel for data, addresses and commands exchanged between the host device and the memory array.

公开(公告)号：US20230153204A1

公开(公告)日：2023-05-18

申请号：US18099800

申请日：2023-01-20

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Daniele Balluchi

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G06F12/02

CPC classification number: G06F11/1068 ,  G06F11/0772 ,  G06F11/3037 ,  G06F12/0238 ,  G06F11/076 ,  G06F2212/7201

Abstract: Methods, systems, and devices for maintenance command interfaces for a memory system are described. A host system and a memory system may be configured according to a shared protocol that supports enhanced management of maintenance operations between the host system and memory system, such as maintenance operations to resolve error conditions at a physical address of a memory system. In some examples, a memory system may initiate maintenance operations based on detections performed at the memory system, and the memory system may provide a maintenance indication for the host system. In some examples, a host system may initiate maintenance operations based on detections performed at the host system. In various examples, the described maintenance signaling may include capability signaling between the host system and memory system, status indications between the host system and memory system, and other maintenance management techniques.

公开(公告)号：US20220342737A1

公开(公告)日：2022-10-27

申请号：US17668210

申请日：2022-02-09

Applicant: Micron Technology, Inc.

Inventor： Luca Porzio ,  Alessandro Orlando ,  Danilo Caraccio ,  Roberto Izzi

IPC: G06F11/07 ,  G06F11/30

Abstract: Methods, systems, and devices for detecting page fault traffic are described. A memory device may execute a self-learning algorithm to determine a priority size for read requests, such as a maximum readahead window size or other size related to page faults in a memory system. The memory device may determine the priority size based at least in part on by tracking how many read requests are received for different sizes of sets of data. Once the priority size is determined, the memory device may detect subsequent read requests for sets of data having the priority size, and the memory device may prioritize or other optimize the execution of such read requests.

公开(公告)号：US20220326887A1

公开(公告)日：2022-10-13

申请号：US17657870

申请日：2022-04-04

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Paolo Amato ,  Daniele Balluchi

IPC: G06F3/06

Abstract: Methods, systems, and devices for log management maintenance operation and command are described. A method may include receiving, at a memory system, a command associated with maintenance for the memory system and indicating to initiate collecting values of a parameter, storing a value of the parameter, and transmitting, to a host system, a message indicating an availability of the value of the parameter based at least in part on storing the value of the parameter. An additional method may include transmitting, to a host system, a message indicating that a quantity of errors for an address of an address space associated with the memory system satisfies a threshold, receiving a command associated with maintenance for the memory system and indicating a retirement of the address, and retiring the address for the address space associated with the memory system based at least in part on receiving the command.