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    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells
    71.
    发明公开
    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells 审中-公开

    公开(公告)号：US20240071931A1

    公开(公告)日：2024-02-29

    申请号：US17900064

    申请日：2022-08-31

    Applicant: Micron Technology, Inc.

    Inventor： Tom George ,  Rita J. Klein ,  Daniel Billingsley ,  Pengyuan Zheng ,  Yongjun Jeff Hu

    IPC: H01L23/535 ,  H01L27/11556 ,  H01L27/11582

    CPC classification number: H01L23/535 ,  H01L27/11556 ,  H01L27/11582

    Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprising channel-material strings extend through the insulative tiers and the conductive tiers. The conductor tier comprises upper conductor material directly above and directly against lower conductor material of different composition from that of the upper conductor material. A through-array-via (TAV) region is included and comprises TAVs individually comprising the upper conductor material, the lower conductor material, and a conducting material that is directly below the conductor tier. The lower conductor material is directly against the conducting material and comprises at least one of (a) and (b), where, (a): a metal-rich refractory metal nitride; and (b): a stoichiometric or non-stoichiometric refractory metal nitride directly above and directly against one of (1), (2), or (3), where: (1): an elemental metal; (2): an alloy of at least two elemental metals; and (3): a metal-rich refractory metal nitride of different composition from that of the stoichiometric or non-stoichiometric refractory metal nitride. Methods are also disclosed.

    Integrated Circuitry Comprising A Memory Array Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells
    72.
    发明公开
    Integrated Circuitry Comprising A Memory Array Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells 审中-公开

    公开(公告)号：US20230422503A1

    公开(公告)日：2023-12-28

    申请号：US18244169

    申请日：2023-09-08

    Applicant: Micron Technology, Inc.

    Inventor： Daniel Billingsley ,  Jordan D. Greenlee ,  John D. Hopkins ,  Yongjun Jeff Hu ,  Swapnil Lengade

    IPC: H10B43/27 ,  H01L21/311 ,  H10B41/27

    CPC classification number: H10B43/27 ,  H01L21/31111 ,  H10B41/27

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming an upper stack directly above a lower stack. The lower stack comprises vertically-alternating lower-first-tiers and lower-second-tiers. The upper stack comprises vertically-alternating upper-first-tiers and upper-second-tiers. Lower channel openings extend through the lower-first-tiers and the lowers-second-tiers. The lower channel openings have sacrificial material therein. An upper of the lower-first-tiers or a lower of the upper-first-tiers comprises non-stoichiometric silicon nitride comprising (a) or (b), where (a): a nitrogen-to-silicon atomic ratio greater than 1.33 and less than 1.5; and (b): a nitrogen-to-silicon atomic ratio greater than or equal to 1.0 and less than 1.33. A higher of the upper-first-tiers that is above said lower upper-first-tier comprises silicon nitride not having either the (a) or the (b). Upper channel openings are etched through the upper-first-tiers and the upper-second-tiers to stop on said upper lower-first-tier or said lower upper-first-tier. After the stop, the sacrificial material is removed from the lower channel openings and form channel-material strings in the upper and lower channel openings. Other embodiments, including structure independent of method, are disclosed.

    Memory arrays and methods used in forming a memory array comprising strings of memory cells
    75.
    发明授权
    Memory arrays and methods used in forming a memory array comprising strings of memory cells 有权

    公开(公告)号：US11569120B2

    公开(公告)日：2023-01-31

    申请号：US17228937

    申请日：2021-04-13

    Applicant: Micron Technology, Inc.

    Inventor： Daniel Billingsley ,  Jordan D. Greenlee ,  Yongjun Jeff Hu

    IPC: H01L21/762 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L21/311 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/3115

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. Bridge material is formed across the trenches laterally-between and longitudinally-along immediately-laterally-adjacent of the memory-block regions. The bridge material comprises longitudinally-alternating first and second regions. The first regions of the bridge material are ion implanted differently than the second regions of the bridge material to change relative etch rate of one of the first or second regions relative to the other in an etching process. The first and second regions are subjected to the etching process to selectively etch away one of the first and second regions relative to the other to form bridges that extend across the trenches laterally-between and longitudinally-spaced-along the immediately-laterally-adjacent memory-block regions. Other embodiments and structure independent of method are disclosed.

    Integrated structures and methods of forming integrated structures
    77.
    发明授权
    Integrated structures and methods of forming integrated structures 有权

    公开(公告)号：US11107823B2

    公开(公告)日：2021-08-31

    申请号：US16684515

    申请日：2019-11-14

    Applicant: Micron Technology, Inc.

    Inventor： Yongjun Jeff Hu ,  Allen McTeer

    IPC: H01L27/11524 ,  H01L21/02 ,  H01L21/322 ,  H01L27/1157 ,  H01L27/11582

    Abstract: Some embodiments include an integrated structure having semiconductor material within a region between two parallel surfaces. The semiconductor material has grain boundaries parallel to the parallel surfaces. At least one circuit component utilizes a region of the semiconductor material in a gated device. The semiconductor material has little if any metal therein so that the gated device has Ion/Ioff characteristics similar to if the semiconductor material had no metal therein. Some embodiments include a method in which semiconductor material is provided between a pair of parallel surfaces, and in which the parallel surfaces and semiconductor material extend between a first end and a second end. Metal is formed adjacent the first end, and gettering material is formed adjacent the second end. Thermal processing induces crystallization of the semiconductor material and drives the metal along the semiconductor material and into the gettering material. The gettering material is then removed.

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