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    MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SHIELD STRUCTURES
    71.
    发明申请
    MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SHIELD STRUCTURES 有权

    公开(公告)号：US20220278112A1

    公开(公告)日：2022-09-01

    申请号：US17186962

    申请日：2021-02-26

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Haitao Liu ,  Karthik Sarpatwari ,  Durai Vishak Nirmal Ramaswamy ,  Alessandro Calderoni ,  Richard E. Fackenthal ,  Duane R. Mills

    IPC: H01L27/1156 ,  H01L29/24 ,  H01L29/786

    Abstract: Some embodiments include apparatuses in which one of such apparatus includes a first memory cell including a first transistor having a first channel region coupled between a data line and a conductive region, and a first charge storage structure located between the first data line and the conductive region, and a second transistor having a second channel region coupled to and located between the first data line and the first charge storage structure; a second memory cell including a third transistor having a third channel region coupled between a second data line and the conductive region, and a second charge storage structure located between the second data line and the conductive region, and a fourth transistor having a fourth channel region coupled to and located between the second data line and the second charge storage structure; a conductive line forming a gate of each of the first, second, third, and fourth transistors; and a conductive structure located between the first and second charge storage structures and electrically separated from the conductive region.

    PERFORMING REFRESH OPERATIONS ON MEMORY CELLS
    72.
    发明申请
    PERFORMING REFRESH OPERATIONS ON MEMORY CELLS 有权

    公开(公告)号：US20220246202A1

    公开(公告)日：2022-08-04

    申请号：US17167922

    申请日：2021-02-04

    Applicant: Micron Technology, Inc.

    Inventor： Karthik Sarpatwari ,  Lingming Yang ,  Nevil N. Gajera ,  John Christopher M. Sancon

    IPC: G11C11/406 ,  G11C11/4074 ,  G11C11/4091

    Abstract: The present disclosure includes apparatuses, methods, and systems for performing refresh operations on memory cells. A memory can include a group of memory cells and one or more additional memory cells whose data state is indicative of whether to refresh the group of memory cells. Circuitry is configured to apply a first voltage pulse to the group of memory cells to sense a data state of the memory cells of the group, apply, while the first voltage pulse is applied to the group of memory cells, a second voltage pulse having a greater magnitude than the first voltage pulse to the one or more additional memory cells to sense a data state of the one or more additional memory cells, and determine whether to perform a refresh operation on the group of memory cells based on the sensed data state of the one or more additional memory cells.

    Techniques for applying multiple voltage pulses to select a memory cell
    73.
    发明授权
    Techniques for applying multiple voltage pulses to select a memory cell 有权

    公开(公告)号：US11367483B2

    公开(公告)日：2022-06-21

    申请号：US17089146

    申请日：2020-11-04

    Applicant: Micron Technology, Inc.

    Inventor： Josephine T. Hamada ,  Mingdong Cui ,  Joseph M. McCrate ,  Karthik Sarpatwari ,  Jessica Chen

    IPC: G11C7/22 ,  G11C13/00 ,  H01L45/00 ,  G11C5/14

    Abstract: Methods, systems, and devices for memory cell selection to enable a memory device to select a targeted memory cell during a write operation are described. The memory device may apply a first pulse to a selected bit line of the targeted memory cell while applying a voltage to deselected word lines to prevent current leakage. If the targeted memory is not selected after the first pulse, the memory device may apply a second pulse to the selected bit line while applying a voltage to the deselected word lines. If the targeted memory cell is not selected following the second pulse, the memory device may apply a third pulse to the selected bit line while applying the voltage to the deselected word lines. The memory device may detect a snapback event after any of the pulses if the targeted memory cell is selected.

    Accessing a multi-level memory cell
    74.
    发明授权
    Accessing a multi-level memory cell 有权

    公开(公告)号：US11355209B2

    公开(公告)日：2022-06-07

    申请号：US16926556

    申请日：2020-07-10

    Applicant: Micron Technology, Inc.

    Inventor： Karthik Sarpatwari ,  Xuan-Anh Tran ,  Jessica Chen ,  Jason A. Durand ,  Nevil N. Gajera ,  Yen Chun Lee

    IPC: G11C16/10 ,  G11C16/34 ,  G11C16/30 ,  G11C16/26

    Abstract: Methods, systems, and devices for accessing a multi-level memory cell are described. The memory device may perform a read operation that includes pre-read portion and a read portion to access the multi-level memory cell. During the pre-read portion, the memory device may apply a plurality of voltages to a plurality of memory cells to identify a likely distribution of memory cells storing a first logic state. During the read portion, the memory device may apply a first read voltage to a memory cell based on performing the pre-read portion. The memory device may apply a second read voltage to the memory cell during the read portion that is based on the first read voltage. The memory device may determine the logic state stored by the memory cell based on applying the first read voltage and the second read voltage.

    Data-based polarity write operations
    77.
    发明授权
    Data-based polarity write operations 有权

    公开(公告)号：US11139034B1

    公开(公告)日：2021-10-05

    申请号：US16929884

    申请日：2020-07-15

    Applicant: Micron Technology, Inc.

    Inventor： Karthik Sarpatwari ,  Nevil N. Gajera ,  Hongmei Wang ,  Mingdong Cui

    IPC: G11C7/00 ,  G11C16/34 ,  G11C16/30 ,  G11C16/26 ,  G11C16/10

    Abstract: Methods, systems, and devices for data-based polarity write operations are described. A write command may cause a set of data to be written to a set of memory cells. To write the set of data, a write operation that applies voltages across the memory cells based on a logic state of data to be written to the memory cells may be used. During a first interval of the write operation, a voltage may be applied across a memory cell based on a logic state of a data bit to be written to the memory cell. During a second interval of the write operation, a voltage may be applied across the memory cell based on an amount of charge conducted by the memory cell during the first interval.

    DIRTY WRITE ON POWER OFF
    79.
    发明申请
    DIRTY WRITE ON POWER OFF 有权

    公开(公告)号：US20210233584A1

    公开(公告)日：2021-07-29

    申请号：US17165555

    申请日：2021-02-02

    Applicant: Micron Technology, Inc.

    Inventor： Karthik Sarpatwari ,  Fabio Pellizzer ,  Jessica Chen ,  Nevil Gajera

    IPC: G11C13/00

    Abstract: Methods, systems, and devices for dirty write on power off are described. In an example, the described techniques may include writing memory cells of a device according to one or more parameters (e.g., reset current amplitude), where each memory cell is associated with a storage element storing a value based on a material property associated with the storage element. Additionally, the described techniques may include identifying, after writing the memory cells, an indication of power down for the device and refreshing, before the power down of the device, a portion of the memory cells based on identifying the indication of the power down for the device. In some cases, refreshing includes modifying at least one of the one or more parameters for a write operation for the portion of the memory cells.

    MEMORY CELL SELECTION
    80.
    发明申请
    MEMORY CELL SELECTION 有权

    公开(公告)号：US20210151107A1

    公开(公告)日：2021-05-20

    申请号：US17089146

    申请日：2020-11-04

    Applicant: Micron Technology, Inc.

    Inventor： Josephine T. Hamada ,  Mingdong Cui ,  Joseph M. McCrate ,  Karthik Sarpatwari ,  Jessica Chen

    IPC: G11C13/00 ,  H01L45/00 ,  G11C5/14

    Abstract: Methods, systems, and devices for memory cell selection to enable a memory device to select a targeted memory cell during a write operation are described. The memory device may apply a first pulse to a selected bit line of the targeted memory cell while applying a voltage to deselected word lines to prevent current leakage. If the targeted memory is not selected after the first pulse, the memory device may apply a second pulse to the selected bit line while applying a voltage to the deselected word lines. If the targeted memory cell is not selected following the second pulse, the memory device may apply a third pulse to the selected bit line while applying the voltage to the deselected word lines. The memory device may detect a snapback event after any of the pulses if the targeted memory cell is selected.

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