-
71.发明申请公开(公告)号：US20210273653A1
公开(公告)日：2021-09-02
申请号：US16806826
申请日：2020-03-02
Applicant: Micron Technology, Inc.
Inventor： Eyal En Gad , Zhengang Chen , Sivagnanam Parthasarathy , Yoav Weinberg
Abstract: A processing device in a memory system reads a sense word from a memory device and executes a plurality of parity check equations on corresponding subsets of the sense word to determine a plurality of parity check equation results. The processing device determines a syndrome for the sense word using the plurality of parity check equation results, determines whether the syndrome for the sense word satisfies a codeword criterion, and responsive to the syndrome for the sense word not satisfying the codeword criterion, performs an iterative low density parity check (LDPC) correction process, wherein at least one criterion of the iterative LDPC correction process is adjusted after a threshold number of iterations is performed.
-
公开(公告)号：US20210011769A1
公开(公告)日：2021-01-14
申请号：US16510426
申请日：2019-07-12
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Tingjun Xie , Zhengang Chen , Zhenlei Shen
IPC: G06F9/50 , G06F12/06 , G11C11/4074
Abstract: An indication that an allocation unit of a memory sub-system has become unmapped can be received. In response to receiving the indication that the allocation unit of the memory sub-system has become unmapped, the allocation unit can be programmed with a data pattern. Data to be written to the unmapped allocation unit can be received. A write operation can be performed to program the received data at the unmapped allocation unit by using a read voltage that is based on the data pattern.
-
公开(公告)号：US10892029B1
公开(公告)日：2021-01-12
申请号：US16510454
申请日：2019-07-12
Applicant: Micron Technology, Inc.
Inventor： Tingjun Xie , Zhengang Chen
Abstract: A processing device in a memory system identifies a first range of a plurality of write-to-read delay ranges for the memory component, wherein the first range represents a plurality of write-to-read delay times and has an associated read voltage level used to perform a read operation on a segment of the memory component having a write-to-read delay time that falls within the first range. The processing device further identifies a first set of the plurality of write-to-read delay times at a first end of the first range and determines a first directional error rate for the memory component corresponding to the first set of the plurality of write-to-read delay times and a second directional error rate for the memory component corresponding to the first set of the plurality of write-to-read delay times. The processing device determines whether a correspondence between the first directional error rate and the second directional error rate satisfies a first threshold criterion and, responsive to the correspondence between the first directional error rate and the second directional error rate not satisfying the first threshold criterion, modifies the read voltage level associated with the first range.
-
公开(公告)号：US10761754B2
公开(公告)日：2020-09-01
申请号：US16057537
申请日：2018-08-07
Applicant: Micron Technology, Inc.
Inventor： Zhenlei E. Shen , Zhengang Chen , Tingjun Xie , Jiangli Zhu
Abstract: Data can be received at a memory sub-system. A characteristic of the memory sub-system can be identified. A read voltage level can be determined based on the characteristic of the memory sub-system. A read operation can be performed at the memory sub-system based on the read voltage level to retrieve stored data. The received data can be stored at the memory sub-system based on the stored data that was retrieved from the read operation that is based on the read voltage level.
-
公开(公告)号：US20200185045A1
公开(公告)日：2020-06-11
申请号：US16215267
申请日：2018-12-10
Applicant: Micron Technology, Inc.
Inventor： Zhengang Chen , Sai Krishna Mylavarapu , Zhenlei Shen , Tingjun Xie , Charles S. Kwong
Abstract: Described herein are embodiments related to defect detection in memory components of memory systems with time-varying bit error rate. A processing device performs an error recovery flow (ERF) to recover a unit of data comprising data and a write timestamp indicating when the unit of data was written. The processing device determines whether to perform a defect detection operation to detect a defect in the memory component using a bit error rate (BER), corresponding to the read operation, and the write timestamp in the unit of data. The processing device initiates the defect detection operation responsive to the BER condition not being expected for the calculated W2R (based on the write timestamp). The processing device can use an ERF condition and the write timestamp to determine whether to perform the defect detection operation. The processing device initiates the defect detection operation responsive to the ERF condition not being expected the calculated W2R (based on the write timestamp).
-
Patent Agency Ranking
公开(公告)号：US20240419332A1
公开(公告)日：2024-12-19
申请号：US18741219
申请日：2024-06-12
Applicant: Micron Technology, Inc.
Inventor： Tomer Eliash , Jianmin Huang , Zhengang Chen
IPC: G06F3/06
Abstract: Aspects of the present disclosure configure a memory sub-system controller to read data from a first portion of a memory based on read levels previously established while reading a second portion of the memory. The controller receives a request to read data from a first portion of a set of memory components. The controller identifies a second portion of the set of memory components that has been programmed with data within a threshold period of time of programming the data in the first portion. The controller retrieves a set of read threshold levels that have been previously computed in association with reading the data from the second portion. The controller reads the data from the first portion using the set of read threshold levels that have been previously computed in association with reading the data from the second portion.
-
公开(公告)号：US20240370185A1
公开(公告)日：2024-11-07
申请号：US18774803
申请日：2024-07-16
Applicant: Micron Technology, Inc.
Inventor： Eyal En Gad , Zhengang Chen , Yoav Weinberg
IPC: G06F3/06
Abstract: A processing device in a memory sub-system receives a request to perform a memory access operation on a memory device, determines a memory segment identifier associated with the memory access operation, and applies a hash function to the memory segment identifier to generate a hashed seed. The processing device further provides the hashed seed to a pseudo-random number generator to generate a randomized string, and performs the memory access operation on the memory device using the randomized string.
-
78.发明公开公开(公告)号：US20240319886A1
公开(公告)日：2024-09-26
申请号：US18421893
申请日：2024-01-24
Applicant: Micron Technology, Inc.
Inventor： Peng Zhang , Lei Lin , Hanping Chen , Li-Te Chang , Zhengang Chen , Murong Lang , Zhenming Zhou
IPC: G06F3/06
CPC classification number: G06F3/0614 , G06F3/0652 , G06F3/0679
Abstract: A method for receiving a request for performing a programming operation on one or more memory blocks of a memory device, identifying a value of a media endurance metric associated with the one or more memory blocks, determining a programming voltage offset corresponding to the value of the media endurance metric, and performing, using the programming voltage offset, the programming operation on the one or more memory blocks. The method further includes identifying a program-verify voltage level associated with the one or more memory blocks, determining a program-verify voltage offset associated with the program-verify voltage level and the value of the media endurance metric, and performing, using the program-verify voltage level and the program-verify voltage offset, a program-verify operation on the one or more memory blocks.
-
公开(公告)号：US20240248612A1
公开(公告)日：2024-07-25
申请号：US18406852
申请日：2024-01-08
Applicant: Micron Technology, Inc.
Inventor： Lei Lin , Peng Zhang , Pitamber Shukla , Zhengang Chen , Zhenming Zhou
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/0659 , G06F3/0679
Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to modify pulses used to program memory components. The controller receives a request to program data in an individual memory component of a set of memory components. The controller computes a plurality of memory reliability criteria associated with the individual memory component and compares the plurality of memory reliability criteria to one or more threshold values. The controller selects a program pulse used to program the data to the individual memory component based on a result of comparing the plurality of memory reliability criteria to the one or more threshold values.
-
公开(公告)号：US12007837B2
公开(公告)日：2024-06-11
申请号：US18230360
申请日：2023-08-04
Applicant: Micron Technology, Inc.
Inventor： Zhengang Chen , Sivagnanam Parthasarathy
CPC classification number: G06F11/1004 , G06F3/0619 , G06F3/0659 , G06F3/0673
Abstract: A method may comprise detecting an error associated with accessing a set of data items. The set of data items are programmed to a respective memory page associated with a stripe of a plurality of stripes. In response to determining that the set of data items comprises one or more codewords, a first data recovery process is performed to recover the one or more codewords based at least in part on RAIN redundancy metadata. In response to determining that the set of data items comprises additional parity metadata, a second data recovery process is performed to recover the additional parity metadata based at least in part on LUN redundancy metadata. In response to determining that the set of data items comprises RAIN redundancy metadata, a first data reconstruction process is performed to regenerate the RAIN redundancy metadata based at least in part on one or more sets of codewords.
-
-
-
-
-
-
-
-
-
Search Results
98
records
(took 0.018 seconds)
