公开(公告)号：US06769044B2

公开(公告)日：2004-07-27

申请号：US10003048

申请日：2001-12-06

申请人： Yasurou Matsuzaki

发明人： Yasurou Matsuzaki

IPC分类号： G06F1314

CPC分类号： H04L25/493 ,  H03M5/02

摘要： A logical value is expressed by an order that transition edges appear in a plurality of transmission signals transmitting respectively on a plurality of signal lines. Otherwise, the logical value is expressed by a time difference between the transition edge of the transmission signal transmitting on the signal line and a transition edge of a standard timing signal. Therefore, a large amount of data can be transmitted through one signal line. Since a large amount of data can be transmitted by one transmission, it is possible to substantially increase the data transfer rate. Since only a small number of the signal lines are necessary, it is possible to reduce the number of input circuits and output circuits of the transmission signals, to reduce power consumption, and to reduce the wiring area of the signal lines.

摘要翻译： 逻辑值由在多个信号线上分别发送的多个发送信号中出现过渡边缘的顺序表示。 否则，逻辑值由在信号线上发送的发送信号的过渡边缘与标准定时信号的过渡边缘之间的时间差表示。 因此，可以通过一条信号线传输大量的数据。 由于通过一次发送可以发送大量数据，因此可以显着增加数据传送速率。 由于仅需要少量的信号线，所以可以减少传输信号的输入电路和输出电路的数量，以减少功耗，并且减少信号线的布线面积。

公开(公告)号：US06628562B2

公开(公告)日：2003-09-30

申请号：US10001790

申请日：2001-12-05

申请人： Toshiya Uchida ,  Yasurou Matsuzaki

发明人： Toshiya Uchida ,  Yasurou Matsuzaki

IPC分类号： G11C800

CPC分类号： G11C7/22 ,  G11C7/1072

摘要： Data is stored into a plurality of first memory blocks, and regeneration data for regenerating this data is stored into a second memory block. In a read operation, either a first operation for reading the data directly from a first memory block selected or a second operation for regenerating the data from the data stored in unselected first memory blocks and the regeneration data stored in the second memory block is performed. This makes it possible to perform an additional read operation on a first memory block during the read operation of this first memory block. Therefore, requests for read operations from exterior can be received at intervals shorter than read cycles. That is, the semiconductor memory can be operated at higher speed, with an improvement in data read rate.

公开(公告)号：US06519171B2

公开(公告)日：2003-02-11

申请号：US09904478

申请日：2001-07-16

申请人： Yasurou Matsuzaki ,  Masao Taguchi

发明人： Yasurou Matsuzaki ,  Masao Taguchi

IPC分类号： G11C502

CPC分类号： G11C7/10 ,  G11C29/48 ,  G11C2207/104

摘要： A semiconductor memory device manufactured separately is connected to an interface unit of a semiconductor device. An internal memory formed in the semiconductor device is connected to at least a part of the interface unit. A memory selecting circuit makes the internal memory accessible in a first operation mode, and makes the internal memory inaccessible in a second operation mode. Therefore, for example, putting the semiconductor device into the first operation mode and accessing the internal memory enables the semiconductor device to operate as a predetermined system even when the semiconductor memory device is not connected to the interface unit. The substitution of the internal memory for the semiconductor memory device makes it possible for the semiconductor device to test the interface unit and associated circuits thereof by itself. This consequently allows improvement in the assembly yield of multichip modules.

公开(公告)号：US06510095B1

公开(公告)日：2003-01-21

申请号：US10073231

申请日：2002-02-13

申请人： Yasurou Matsuzaki ,  Hiroyoshi Tomita ,  Masao Taguchi

发明人： Yasurou Matsuzaki ,  Hiroyoshi Tomita ,  Masao Taguchi

IPC分类号： G11C700

CPC分类号： G11C7/109 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C2207/2227

摘要： A command receiver circuit receives a command signal in synchronization with either a rising edge or a falling edge of a clock signal. A data input/output circuit starts an output of read data and an input of write data in synchronization with the edges of the clock signal which are set in response to reception timing of the command signal. Since the command signal can be received in synchronization with both edges of the clock signal, it is possible to halve a clock cycle when a reception rate is the same as that of the conventional art. As a result of this, in a system on which the semiconductor memory device is mounted, it is possible to halve the frequency of a system clock and to reduce power consumption of a clock synchronization circuit in the system, without reducing a data input/output rate for the semiconductor memory device.

摘要翻译： 命令接收器电路与时钟信号的上升沿或下降沿同步地接收命令信号。 数据输入/输出电路与响应命令信号的接收定时而设置的时钟信号的边沿同步地开始读取数据的输出和写入数据的输入。 由于可以与时钟信号的两个边沿同步地接收命令信号，所以当接收速率与传统技术的接收速率相同时，可以将时钟周期减半。 结果，在安装了半导体存储器件的系统中，可以将系统时钟的频率减半，并且可以降低系统中时钟同步电路的功耗，而不减少数据输入/输出 速率为半导体存储器件。

公开(公告)号：US06272069B1

公开(公告)日：2001-08-07

申请号：US09764446

申请日：2001-01-19

申请人： Hiroyoshi Tomita ,  Yasurou Matsuzaki ,  Masao Taguchi

发明人： Hiroyoshi Tomita ,  Yasurou Matsuzaki ,  Masao Taguchi

IPC分类号： G11C800

摘要： A data signal is output from an output circuit of a first chip and sent to a data input terminal in the second chip via a data lead line based on an output clock in first chip, which is sent to the second chip. And an input circuit in a second chip receives the data signal and transfers it inside in response to a transfer clock that has been generated from the output clock in the first chip. In synchronism with a single reference clock in the first chip, therefore, a data signal can be transferred to the second chip from the first chip at a high speed.

公开(公告)号：US06215714B1

公开(公告)日：2001-04-10

申请号：US09517279

申请日：2000-03-02

申请人： Yoshihiro Takemae ,  Yasurou Matsuzaki

发明人： Yoshihiro Takemae ,  Yasurou Matsuzaki

IPC分类号： G11C700

CPC分类号： G11C11/40622 ,  G11C11/406

摘要： A semiconductor memory device, which refreshes memory cells to retain data, has a first refresh mode and a second refresh mode. The first refresh mode is a mode for refreshing all of the memory cells, and the second refresh mode is a mode for refreshing a part of the memory cells. By refreshing only designated areas where data must be retained, power consumption in a refresh operation can be reduced, drastically cutting power consumption in a power-down mode.

摘要翻译： 刷新存储单元以保留数据的半导体存储器件具有第一刷新模式和第二刷新模式。 第一刷新模式是用于刷新所有存储单元的模式，第二刷新模式是用于刷新存储单元的一部分的模式。 通过仅刷新必须保留数据的指定区域，可以减少刷新操作中的功耗，从而在掉电模式下大幅度地削减功耗。

公开(公告)号：US06198689B1

公开(公告)日：2001-03-06

申请号：US09440667

申请日：1999-11-16

申请人： Masafumi Yamazaki ,  Hiroyoshi Tomita ,  Yasurou Matsuzaki

发明人： Masafumi Yamazaki ,  Hiroyoshi Tomita ,  Yasurou Matsuzaki

IPC分类号： G11C800

CPC分类号： G11C7/222 ,  G11C7/1072 ,  G11C7/22

摘要： The present invention is an integrated circuit device having a self timing control circuit for generating an input loading timing signal whose phase is adjusted with an external clock, where loading of input signals supplied from outside, such as a command input signal, address input signal and data input signal, to internal circuits is forbidden when the self timing control circuit is adjusting phase. And when the self timing control circuit finishes adjusting the phase to a certain degree, the loading operation of an input signal at the input circuit using the input loading timing signal is enabled. To execute such an operation, the input circuit generates an input loading control signal based on a lock-on signal or adjustment signal of the DLL circuit, or based on an input stop cancellation signal, for example. The input circuit controls the stop and restart of loading of the input signal according to this input loading control signal.

摘要翻译： 本发明是一种具有自定时控制电路的集成电路装置，该自定时控制电路用于产生输入负载定时信号，该输入负载定时信号的相位是用外部时钟调整的，其中从外部输入的输入信号如命令输入信号，地址输​​入信号和 数据输入信号，当自定时控制电路正在调整相位时，禁止内部电路。 并且当自定时控制电路在一定程度上完成相位调整时，可以使用输入负载定时信号在输入电路处的输入信号的加载操作。 为了执行这种操作，输入电路基于例如DLL电路的锁定信号或调整信号，或者基于输入停止消除信号，生成输入负载控制信号。 输入电路根据该输入负载控制信号控制输入信号的停止和重新启动。

公开(公告)号：US06194932B1

公开(公告)日：2001-02-27

申请号：US09383015

申请日：1999-08-25

申请人： Yoshihiro Takemae ,  Yasurou Matsuzaki ,  Hiroyoshi Tomita ,  Nobutaka Taniguchi

发明人： Yoshihiro Takemae ,  Yasurou Matsuzaki ,  Hiroyoshi Tomita ,  Nobutaka Taniguchi

IPC分类号： H03L700

CPC分类号： G11C7/222 ,  G06F1/10 ,  G11C7/22 ,  H03L7/0814

摘要： The present invention omits a variable delay circuit (10 in FIG. 1) inside a DLL circuit, and instead, creates a timing synchronization circuit, which generates a second reference clock. The timing synchronization circuit shifts the phase of a first reference clock generated by a frequency divider to the timing of a timing signal generated from the other variable delay circuit so that the second reference clock matches to the timing signal. Then, a phase comparator compares the divided first reference clock to a variable clock that delays the second reference clock, and controls the delay time of the variable delay circuit so that both clocks are in phase. As a result, one variable delay circuit can be omitted, and a DLL circuit that uses a divided clock can be configured.

摘要翻译： 本发明省略了DLL电路内部的可变延迟电路（图1中的10），而是产生产生第二参考时钟的定时同步电路。 定时同步电路将由分频器产生的第一参考时钟的相位移位到从另一个可变延迟电路产生的定时信号的定时，使得第二参考时钟与定​​时信号相匹配。 然后，相位比较器将分频的第一参考时钟与延迟第二参考时钟的可变时钟进行比较，并且控制可变延迟电路的延迟时间，使得两个时钟同相。 结果，可以省略一个可变延迟电路，并且可以配置使用分频时钟的DLL电路。

公开(公告)号：US06181174B2

公开(公告)日：2001-01-30

申请号：US09404221

申请日：1999-09-23

申请人： Waichirou Fujieda ,  Yasuharu Sato ,  Nobutaka Taniguchi ,  Hiroyoshi Tomita ,  Yasurou Matsuzaki

发明人： Waichirou Fujieda ,  Yasuharu Sato ,  Nobutaka Taniguchi ,  Hiroyoshi Tomita ,  Yasurou Matsuzaki

IPC分类号： H03L706

CPC分类号： H03L7/0805 ,  G06F1/08 ,  G06F1/10 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  H03K5/133 ,  H03K23/58 ,  H03L7/0814

摘要： A semiconductor integrated circuit device includes a DLL circuit. The DLL circuit includes a frequency divider which frequency-divides an input clock at a frequency dividing ratio which is varied depending on a frequency of the input clock and thus results in a dummy clock and a reference clock. A delay system includes a variable delay circuit which delays the dummy clock. A control circuit controls a delay amount of the variable delay circuit so that a phase of a delayed dummy clock from the delay system and the reference clock becomes zero.

摘要翻译： 半导体集成电路装置包括DLL电路。 DLL电路包括分频器，该分频器以分频比对输入时钟进行分频，该分频比根据输入时钟的频率而变化，从而产生虚拟时钟和参考时钟。 延迟系统包括延迟虚拟时钟的可变延迟电路。 控制电路控制可变延迟电路的延迟量，使得来自延迟系统和参考时钟的延迟的虚拟时钟的相位变为零。

公开(公告)号：US6133781A

公开(公告)日：2000-10-17

申请号：US349110

申请日：1999-07-08

申请人： Yasuhiro Fujii ,  Yasurou Matsuzaki

发明人： Yasuhiro Fujii ,  Yasurou Matsuzaki

IPC分类号： G11C11/401 ,  G05F3/02 ,  G11C11/407 ,  H01L21/8238 ,  H01L27/092

CPC分类号： G11C11/4097 ,  G11C11/4094 ,  G11C7/12 ,  G11C7/18

摘要： A switch 17 for short-circuiting is connected between the outputs of circuits 15 and 16 each of which outputs a pair of complementary signals .0.S1 and .0.R1. The circuits 15 and 16, and the switch 17 are controlled by a changeover control circuit 18 in response to an input signal .0.A1. To effectively utilizes electric charge which has become unnecessary on a complementary signal line pair, the circuit 18 comprises an edge detecting circuit for providing a pulse to the switch 17 to make it on in response to the edge of the signal .0.A1, and a state control circuit for making the outputs of the circuits 15 and 16 in a high impedance state while the switch 17 being on, and for making the logic states of the signals .0.S1 and .0.R1 completely transit in response to disappearance of the pulse while the switch 17 being off.

摘要翻译： 用于短路的开关17连接在各自输出一对互补信号OS1和OR1的电路15和16的输出之间。 响应于输入信号OA1，电路15和16以及开关17由转换控制电路18控制。 为了有效地利用在互补信号线对上变得不必要的电荷，电路18包括边缘检测电路，用于向开关17提供脉冲以使其响应于信号OA1的边缘而导通，并且状态控制 当开关17接通时使电路15和16的输出处于高阻抗状态，并且用于使信号OS1和OR1的逻辑状态响应于开关17断开时的脉冲消失而完全转变的电路 。