公开(公告)号：US06185149B2

公开(公告)日：2001-02-06

申请号：US09340147

申请日：1999-06-28

申请人： Shinya Fujioka ,  Masao Taguchi ,  Yasuharu Sato ,  Takaaki Suzuki ,  Tadao Aikawa ,  Yasurou Matsuzaki ,  Toshiya Uchida

发明人： Shinya Fujioka ,  Masao Taguchi ,  Yasuharu Sato ,  Takaaki Suzuki ,  Tadao Aikawa ,  Yasurou Matsuzaki ,  Toshiya Uchida

IPC分类号： G11C800

CPC分类号： G11C7/1018 ,  G11C7/1072

摘要： A semiconductor memory includes memory cell blocks, a burst-length information generating circuit which generates burst-length information based on a burst length, and a block enable circuit which receives the burst-length information. The block enable circuit selectively enables one of the memory cell blocks when the burst length is equal to or shorter than a predetermined burst length and selectively enables a plurality of memory cell blocks based on the burst length when the burst length is longer than the predetermined burst length. Data are read from the above-mentioned one or plurality of memory cell blocks.

摘要翻译： 半导体存储器包括存储单元块，基于突发长度生成突发长度信息的突发长度信息产生电路，以及接收脉冲串长度信息的块使能电路。 当突发长度等于或小于预定突发长度时，块使能电路选择性地启用存储单元块中的一个，并且当突发长度长于预定突发时，基于脉冲串长度选择性地启用多个存储单元块 长度。 从上述一个或多个存储单元块读取数据。

公开(公告)号：US6078210A

公开(公告)日：2000-06-20

申请号：US172092

申请日：1998-10-14

申请人： Toshiya Uchida ,  Yasurou Matsuzaki

发明人： Toshiya Uchida ,  Yasurou Matsuzaki

IPC分类号： G01R31/26 ,  G01R31/28 ,  G01R31/30 ,  G05F1/56 ,  G11C11/401 ,  G11C11/407 ,  G11C11/413 ,  G11C16/06 ,  G11C29/06 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04 ,  H02J3/38

CPC分类号： G01R31/3004

摘要： The present invention relates to an internal voltage generating circuit. The internal voltage generating circuit comprises a reference voltage generating circuit for generating a reference voltage, which does not depend on an external power supply; and a comparator including a first input terminal, to which the reference voltage is supplied, a second input terminal, for comparing the voltages of the first and second input terminals and generating an output voltage according to the difference thereof at the output terminal; and an impedance element, which is selectively inserted between the output terminal and the second input terminal of the comparator according to an operation mode. An internal power supply voltage, which has a constant voltage during normal operation and has an accurate higher voltage during acceleration test, can be generated at the output terminal by inserting or not inserting a suitable impedance element between the second input terminal and output terminal according to the operation mode. The above-described comparator can be realized by a common differential amplifying circuit, for example. Further, a reference voltage value at normal operation can be fine-tuned by subdividing the impedance element. In the same way, the voltage value at acceleration test can be also fine-tuned by subdividing the impedance element.

摘要翻译： 本发明涉及内部电压发生电路。 内部电压产生电路包括用于产生不依赖于外部电源的参考电压的参考电压产生电路; 以及比较器，包括提供参考电压的第一输入端，第二输入端，用于比较第一和第二输入端的电压，并根据输出端的差异产生输出电压; 以及阻抗元件，其根据操作模式选择性地插入在比较器的输出端子和第二输入端子之间。 根据本发明，可以在输出端子上插入或不插入合适的阻抗元件，在正常工作期间具有恒定电压并且在加速度测试期间具有准确的较高电压的内部电源电压 操作模式。 上述比较器例如可以由公共差分放大电路实现。 此外，正常工作时的参考电压值可通过细分阻抗元件进行微调。 以同样的方式，加速度测试时的电压值也可以通过细分阻抗元件进行微调。

公开(公告)号：US06774655B2

公开(公告)日：2004-08-10

申请号：US10622472

申请日：2003-07-21

申请人： Yasurou Matsuzaki ,  Masao Nakano ,  Toshiya Uchida ,  Atsushi Hatakeyama ,  Kenichi Kawasaki ,  Yasuhiro Fujii

发明人： Yasurou Matsuzaki ,  Masao Nakano ,  Toshiya Uchida ,  Atsushi Hatakeyama ,  Kenichi Kawasaki ,  Yasuhiro Fujii

IPC分类号： G01R3102

CPC分类号： G11C29/022 ,  G11C29/02

摘要： A semiconductor device mounted on a board or the like and having a test circuit, having the function of carrying out a contact test at a low cost on the terminals of the semiconductor, is disclosed. The semiconductor device comprises a terminal test circuit for testing a state of a contact of an external terminal and a test mode control circuit unit. The test mode control circuit unit outputs a signal indicating a first operation mode upon application of a power supply voltage thereto, outputs a test mode signal to the terminal test circuit in response to a control signal input to a specific terminal such as a chip select terminal, and outputs a signal indicating a second operation mode in response to the number of times in which the level of the control signal input to the specific terminal changes. Preferably, the first operation mode is a terminal test mode, and the second operation mode is a normal operation mode. A method of testing the semiconductor device and a semiconductor integrated circuit, having the test circuit, are also disclosed.

摘要翻译： 公开了一种安装在板等上并具有测试电路的半导体器件，具有在半导体端子上以低成本进行接触测试的功能。 半导体器件包括用于测试外部端子和测试模式控制电路单元的接触状态的端子测试电路。 测试模式控制电路单元在施加电源电压时输出指示第一操作模式的信号，响应于输入到诸如芯片选择端子的特定终端的控制信号，向终端测试电路输出测试模式信号 并且响应于输入到特定终端的控制信号的电平改变的次数而输出指示第二操作模式的信号。 优选地，第一操作模式是终端测试模式，并且第二操作模式是正常操作模式。 还公开了一种测试半导体器件的方法和具有测试电路的半导体集成电路。

公开(公告)号：US06636444B2

公开(公告)日：2003-10-21

申请号：US10057976

申请日：2002-01-29

申请人： Toshiya Uchida ,  Yasurou Matsuzaki

发明人： Toshiya Uchida ,  Yasurou Matsuzaki

IPC分类号： G11C1604

CPC分类号： G11C7/1087 ,  G11C7/1078 ,  G11C8/06

摘要： A semiconductor memory device has a read data line, a write data line, a data holding circuit, and a data writing circuit. The data holding circuit holds data on the write data line, and the data writing circuit writes the data held on the write data line into a memory cell. Further, a semiconductor memory device has a read data line, a write data line, and an address information holding circuit. The address information holding circuit holds address information that is input in relation to write data, and when an access occurs to the address held in the address information holding circuit, data held on the write data line is written into a memory cell corresponding to the address.

公开(公告)号：US06621283B1

公开(公告)日：2003-09-16

申请号：US09437221

申请日：1999-11-10

申请人： Yasurou Matsuzaki ,  Masao Nakano ,  Toshiya Uchida ,  Atsushi Hatakeyama ,  Kenichi Kawasaki ,  Yasuhiro Fujii

发明人： Yasurou Matsuzaki ,  Masao Nakano ,  Toshiya Uchida ,  Atsushi Hatakeyama ,  Kenichi Kawasaki ,  Yasuhiro Fujii

IPC分类号： G01R3102

CPC分类号： G11C29/022 ,  G11C29/02

摘要： A semiconductor device mounted on a board or the like and having a test circuit, having the function of carrying out a contact test at a low cost on the terminals of the semiconductor, is disclosed. The semiconductor device comprises a terminal test circuit for testing a state of a contact of an external terminal and a test mode control circuit unit. The test mode control circuit unit outputs a signal indicating a first operation mode upon application of a power supply voltage thereto, outputs a test mode signal to the terminal test circuit in response to a control signal input to a specific terminal such as a chip select terminal, and outputs a signal indicating a second operation mode in response to the number of times in which the level of the control signal input to the specific terminal changes. Preferably, the first operation mode is a terminal test mode, and the second operation mode is a normal operation mode. A method of testing the semiconductor device and a semiconductor integrated circuit, having the test circuit, are also disclosed.

摘要翻译： 公开了一种安装在板等上并具有测试电路的半导体器件，具有在半导体端子上以低成本进行接触测试的功能。 半导体器件包括用于测试外部端子和测试模式控制电路单元的接触状态的端子测试电路。 测试模式控制电路单元在施加电源电压时输出指示第一操作模式的信号，响应于输入到诸如芯片选择端子的特定终端的控制信号，向终端测试电路输出测试模式信号 并且响应于输入到特定终端的控制信号的电平改变的次数而输出指示第二操作模式的信号。 优选地，第一操作模式是终端测试模式，并且第二操作模式是正常操作模式。 还公开了一种测试半导体器件的方法和具有测试电路的半导体集成电路。

公开(公告)号：US06359813B1

公开(公告)日：2002-03-19

申请号：US09644547

申请日：2000-08-24

申请人： Toshiya Uchida ,  Yasurou Matsuzaki

发明人： Toshiya Uchida ,  Yasurou Matsuzaki

IPC分类号： G11C1604

CPC分类号： G11C7/1087 ,  G11C7/1078 ,  G11C8/06

摘要： A semiconductor memory device has a read data line, a write data line, a data holding circuit, and a data writing circuit. The data holding circuit holds data on the write data line, and the data writing circuit writes the data held on the write data line into a memory cell. Further, a semiconductor memory device has a read data line, a write data line, and an address information holding circuit. The address information holding circuit holds address information that is input in relation to write data, and when an access occurs to the address held in the address information holding circuit, data held on the write data line is written into a memory cell corresponding to the address.

公开(公告)号：US06628562B2

公开(公告)日：2003-09-30

申请号：US10001790

申请日：2001-12-05

申请人： Toshiya Uchida ,  Yasurou Matsuzaki

发明人： Toshiya Uchida ,  Yasurou Matsuzaki

IPC分类号： G11C800

CPC分类号： G11C7/22 ,  G11C7/1072

摘要： Data is stored into a plurality of first memory blocks, and regeneration data for regenerating this data is stored into a second memory block. In a read operation, either a first operation for reading the data directly from a first memory block selected or a second operation for regenerating the data from the data stored in unselected first memory blocks and the regeneration data stored in the second memory block is performed. This makes it possible to perform an additional read operation on a first memory block during the read operation of this first memory block. Therefore, requests for read operations from exterior can be received at intervals shorter than read cycles. That is, the semiconductor memory can be operated at higher speed, with an improvement in data read rate.

公开(公告)号：US6078514A

公开(公告)日：2000-06-20

申请号：US61023

申请日：1998-04-16

申请人： Yoshihiro Takemae ,  Masao Taguchi ,  Masao Nakano ,  Takaaki Suzuki ,  Hiroyoshi Tomita ,  Toshiya Uchida ,  Yasuharu Sato ,  Atsushi Hatakeyama ,  Masato Matsumiya ,  Yasurou Matsuzaki

发明人： Yoshihiro Takemae ,  Masao Taguchi ,  Masao Nakano ,  Takaaki Suzuki ,  Hiroyoshi Tomita ,  Toshiya Uchida ,  Yasuharu Sato ,  Atsushi Hatakeyama ,  Masato Matsumiya ,  Yasurou Matsuzaki

IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  H01L21/60 ,  H01L25/00 ,  H01L27/10 ,  H01L25/04 ,  H01L23/36

CPC分类号： H01L23/60 ,  G11C7/1006 ,  G11C7/22 ,  H01L24/49 ,  H01L25/0655 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L24/48 ,  H01L27/0266 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/30105

摘要： A semiconductor system includes at least one logic chip and at least one memory chip arranged such that one side of the at least one memory chip faces one side of the at least one logic chip. The semiconductor system further includes first input/output nodes, provided for the at least one logic chip, for data transfer with an adjacent memory chip, second input/output nodes, provided for the at least one memory chip, for data transfer with an adjacent logic chip, and a package housing the at least one logic chip and the at least one memory chip, wherein the first input/output nodes are arranged along the one side of the at least one logic chip, and the second input/output nodes are arranged along the one side of the at least one memory chip.

摘要翻译： 半导体系统包括至少一个逻辑芯片和布置成使得至少一个存储器芯片的一侧面向至少一个逻辑芯片的一侧的至少一个存储器芯片。 所述半导体系统还包括为所述至少一个逻辑芯片提供的用于与相邻存储器芯片进行数据传输的第一输入/输出节点，为所述至少一个存储器芯片提供的第二输入/输出节点，用于与相邻的 逻辑芯片以及容纳所述至少一个逻辑芯片和所述至少一个存储器芯片的封装，其中所述第一输入/输出节点沿着所述至少一个逻辑芯片的一侧布置，并且所述第二输入/输出节点是 沿着至少一个存储器芯片的一侧布置。

公开(公告)号：US20080285375A1

公开(公告)日：2008-11-20

申请号：US12124765

申请日：2008-05-21

申请人： Yasurou Matsuzaki

发明人： Yasurou Matsuzaki

IPC分类号： G11C8/18 ,  H03L7/00

CPC分类号： G11C7/1057 ,  G06F1/10 ,  G06F5/06 ,  G11C5/063 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222 ,  H03L7/07 ,  H03L7/081

摘要： A module includes a semiconductor device, a phase adjustment circuit generating a second clock so that a phase adjustment signal output from the semiconductor device and a first clock have a predetermined phase relationship, and an output circuit that is provided in the semiconductor device and generates the phase adjustment signal from the second clock.

摘要翻译： 模块包括半导体器件，产生第二时钟的相位调整电路，使得从半导体器件输出的相位调整信号和第一时钟具有预定的相位关系，以及设置在半导体器件中的输出电路， 来自第二个时钟的相位调整信号。

公开(公告)号：US07345942B2

公开(公告)日：2008-03-18

申请号：US11413204

申请日：2006-04-28

申请人： Yasurou Matsuzaki

发明人： Yasurou Matsuzaki

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/4072 ,  G11C11/4094 ,  G11C2211/4061 ,  G11C2211/4065

摘要： According to the present invention, a memory circuit requiring refresh operations a first circuit which receives a command in synchronization with a clock signal, and which generates a first internal command internally and a second circuit which generates a second internal command, e.g., a refresh command, internally in a prescribed refresh cycle. And an internal circuit, according to said first internal command, executes corresponding control through clock-synchronous operations, and when said refresh command is issued, sequentially executes control corresponding to the refresh command and control corresponding to said first internal command through clock-asynchronous operations. According to the present invention, when a refresh timing signal is generated, the refresh operation can be intrupted among the external command operations.

摘要翻译： 根据本发明，一种需要刷新操作的存储电路，第一电路接收与时钟信号同步的命令，并且内部产生第一内部命令，第二电路产生第二内部命令，例如刷新命令 在规定的刷新周期内部。 并且根据所述第一内部命令，内部电路通过时钟同步操作执行相应的控制，并且当发出所述刷新命令时，通过时钟异步操作顺序执行对应于刷新命令的控制和对应于所述第一内部命令的控制 。 根据本发明，当产生刷新定时信号时，可以在外部命令操作中中断刷新操作。