公开(公告)号：US20100142107A1

公开(公告)日：2010-06-10

申请号：US12656495

申请日：2010-02-01

申请人： Ming-Dou Ker ,  Yuan-Wen Hsiao ,  Ryan Hsin-Chin Jiang

发明人： Ming-Dou Ker ,  Yuan-Wen Hsiao ,  Ryan Hsin-Chin Jiang

IPC分类号： H02H9/04

CPC分类号： H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ESD protection circuit is provided. The circuit includes a discharging component, a diode, and an ESD detection circuit. The discharging component is coupled between an input/output pad and a first power line of an IC. The diode is coupled between the input/output pad and a second power line of the IC in a forward direction toward the second power line. The ESD detection circuit includes a capacitor, a resistor, and a triggering component. The capacitor and the resistor are formed in series and coupled between the first power line and the second power line. The triggering component has a positive power end coupled to the input/output pad and a negative power end coupled to the first power line. An input of the triggering component is coupled to a node between the capacitor and the resistor.

公开(公告)号：US07656627B2

公开(公告)日：2010-02-02

申请号：US11826634

申请日：2007-07-17

申请人： Ming-Dou Ker ,  Yuan-Wen Hsiao ,  Ryan Hsin-Chin Jiang

发明人： Ming-Dou Ker ,  Yuan-Wen Hsiao ,  Ryan Hsin-Chin Jiang

IPC分类号： H02H9/00

CPC分类号： H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ESD protection circuit is provided. The circuit includes a discharging component, a diode, and an ESD detection circuit. The discharging component is coupled between an input/output pad and a first power line of an IC. The diode is coupled between the input/output pad and a second power line of the IC in a forward direction toward the second power line. The ESD detection circuit includes a capacitor, a resistor, and a triggering component. The capacitor and the resistor are formed in series and coupled between the first power line and the second power line. The triggering component has a positive power end coupled to the input/output pad and a negative power end coupled to the first power line. An input of the triggering component is coupled to a node between the capacitor and the resistor.

摘要翻译： 提供ESD保护电路。 电路包括放电元件，二极管和ESD检测电路。 放电元件耦合在IC的输入/输出焊盘和第一电源线之间。 所述二极管在所述输入/输出焊盘和所述IC的第二电源线之间朝向所述第二电力线向前方连接。 ESD检测电路包括电容器，电阻器和触发部件。 电容器和电阻器串联形成并耦合在第一电源线和第二电源线之间。 触发组件具有耦合到输入/输出焊盘的正功率端和耦合到第一电源线的负功率端。 触发元件的输入耦合到电容器和电阻器之间的节点。

公开(公告)号：US20090273006A1

公开(公告)日：2009-11-05

申请号：US12149287

申请日：2008-04-30

申请人： Wen-Yi Chen ,  Ryan Hsin-Chin Jiang ,  Ming-Dou Ker

发明人： Wen-Yi Chen ,  Ryan Hsin-Chin Jiang ,  Ming-Dou Ker

IPC分类号： H01L29/72

CPC分类号： H01L29/747 ,  H01L27/0262 ,  H01L29/87

摘要： The present invention discloses a bidirectional silicon-controlled rectifier, wherein the conventional field oxide layer, which separates an anode structure from a cathode structure, is replaced by a field oxide layer having floating gates, a virtual gate or a virtual active region. Thus, the present invention can reduce or escape from the bird's beak effect of a field oxide layer, which results in crystalline defects, a concentrated current and a higher magnetic field and then causes abnormal operation of a rectifier. Thereby, the present invention can also reduce signal loss.

摘要翻译： 本发明公开了一种双向硅控整流器，其中将阳极结构与阴极结构分开的常规场氧化物层由具有浮动栅极，虚拟栅极或虚拟有源区域的场氧化物层代替。 因此，本发明可以减少或逃避场氧化物层的鸟喙作用，这导致晶体缺陷，集中电流和较高的磁场，然后导致整流器的异常操作。 由此，本发明也可以减少信号损失。

公开(公告)号：US20090236631A1

公开(公告)日：2009-09-24

申请号：US12076556

申请日：2008-03-20

申请人： Wen-Yi Chen ,  Ryan Hsin-Chin Jiang ,  Ming-Dou Ker

发明人： Wen-Yi Chen ,  Ryan Hsin-Chin Jiang ,  Ming-Dou Ker

IPC分类号： H01L29/747

CPC分类号： H01L27/0262 ,  H01L29/747 ,  H01L29/87

摘要： The present invention discloses a bidirectional PNPN silicon-controlled rectifier comprising: a p-type substrate; a N-type epitaxial layer; a P-type well and two N-type wells all formed inside the N-type epitaxial layer with the two N-type wells respectively arranged at two sides of the P-type well; a first semiconductor area, a second semiconductor area and a third semiconductor area all formed inside the P-type well and all coupled to an anode, wherein the second semiconductor area and the third semiconductor area are respectively arranged at two sides of the first semiconductor area, and wherein the first semiconductor area is of first conduction type, and the second semiconductor area and the third semiconductor area are of second conduction type; and two P-type doped areas respectively formed inside the N-type wells, wherein each P-type doped area has a fourth semiconductor area neighboring the P-type well and a fifth semiconductor area, and wherein both the fourth semiconductor area and the fifth semiconductor area are coupled to a cathode, and wherein the fourth semiconductor area is of second conduction type, and the fifth semiconductor area is of first conduction type.

摘要翻译： 本发明公开了一种双向PNPN可控硅整流器，包括：p型衬底; N型外延层; 所有形成在N型外延层内的P型阱和两个N型阱，两个N型阱分别布置在P型阱的两侧; 所述第一半导体区域，第二半导体区域和第三半导体区域全部形成在所述P型阱内并全部耦合到阳极，其中所述第二半导体区域和所述第三半导体区域分别布置在所述第一半导体区域的第二半导体区域 并且其中所述第一半导体区域是第一导电类型，并且所述第二半导体区域和所述第三半导体区域是第二导电类型; 分别形成在N型阱内部的两个P型掺杂区域，其中每个P型掺杂区域具有与P型阱相邻的第四半导体区域和第五半导体区域，并且其中第四半导体区域和第五半导体区域 半导体区域耦合到阴极，并且其中第四半导体区域是第二导电类型，并且第五半导体区域是第一导电类型。

公开(公告)号：US20090009916A1

公开(公告)日：2009-01-08

申请号：US12114485

申请日：2008-05-02

申请人： Ming-Dou Ker ,  Kuo-Chun Hsu ,  Hsin-Chin Jiang

发明人： Ming-Dou Ker ,  Kuo-Chun Hsu ,  Hsin-Chin Jiang

IPC分类号： H02H3/22

CPC分类号： H01L27/0266

摘要： An electrostatic discharge protection circuit that includes at least two transistors connected in a stacked configuration, a first diffusion region of a first dopant type shared by two adjacent transistors, and a second diffusion region of a second dopant type formed in the first diffusion region. A substrate-triggered site is induced into the device structure of the stacked transistors to improve ESD robustness and turn-on speed. An area-efficient layout to realize the stacked transistors is proposed. The stacked transistors may be implemented in ESD protection circuits with a mixed-voltage I/O interface, or in integrated circuits with multiple power supplies. The stacked transistors are fabricated without using a thick-gate mask.

摘要翻译： 一种静电放电保护电路，其包括以堆叠结构连接的至少两个晶体管，由两个相邻晶体管共享的第一掺杂剂类型的第一扩散区域和形成在第一扩散区域中的第二掺杂剂类型的第二扩散区域。 衬底触发位置被引入堆叠晶体管的器件结构，以提高ESD稳健性和开启速度。 提出了实现堆叠晶体管的区域效率布局。 堆叠晶体管可以在具有混合电压I / O接口的ESD保护电路中或在具有多个电源的集成电路中实现。 在不使用厚栅掩模的情况下制造堆叠晶体管。

公开(公告)号：US20090002028A1

公开(公告)日：2009-01-01

申请号：US11769716

申请日：2007-06-28

申请人： Ming-Dou Ker ,  Hui-Wen Tsai ,  Ryan Hsin-Chin Jiang

发明人： Ming-Dou Ker ,  Hui-Wen Tsai ,  Ryan Hsin-Chin Jiang

IPC分类号： H03K19/0175

CPC分类号： H03K19/00315

摘要： A Mixed-voltage input and output (I/O) buffer including a pre-driver unit, a bulk-voltage generating unit, a first to a third transistors and an input stage unit is provided. The pre-driver unit outputs a first source/drain and a second signal. The bulk-voltage generating unit determines whether a first voltage or a pad voltage is used as a bulk voltage according to the pad voltage level. A gate of the first transistor receives the first signal, and a bulk, a first source/drain and a second source/drain of the first transistor are respectively coupled to the bulk voltage, the first voltage and the pad. A gate of the third transistor receives the second signal, and a first source/drain and a second source/drain of the third transistor are respectively coupled to the input stage unit for receiving an input signal from the pad and a second voltage.

摘要翻译： 提供了包括预驱动器单元，体电压产生单元，第一至第三晶体管和输入级单元的混合电压输入和输出（I / O）缓冲器。 预驱动器单元输出第一源极/漏极和第二信号。 体积电压产生单元根据焊盘电压电平来确定是否使用第一电压或焊盘电压作为体电压。 第一晶体管的栅极接收第一信号，并且第一晶体管的体，第一源极/漏极和第二源极/漏极分别耦合到体电压，第一电压和焊盘。 第三晶体管的栅极接收第二信号，第三晶体管的第一源极/漏极和第二源极/漏极分别耦合到输入级单元，用于从焊盘接收输入信号和第二电压。

公开(公告)号：US06747501B2

公开(公告)日：2004-06-08

申请号：US09903547

申请日：2001-07-13

申请人： Ming-Dou Ker ,  Kei-Kang Hung ,  Hsin-Chin Jiang

发明人： Ming-Dou Ker ,  Kei-Kang Hung ,  Hsin-Chin Jiang

IPC分类号： H03K508

CPC分类号： H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit that includes a signal pad, a clamping circuit including a first NMOS transistor having a drain, a source, a gate and a substrate, wherein the drain of the first NMOS transistor is coupled to the signal pad and the source of the first NMOS transistor is coupled to ground, and a control circuit coupled to the gate and substrate of the first NMOS transistor and the signal pad, the control circuit providing a first bias voltage signal to the gate and a second bias voltage signal to the substrate. The voltage level of the first bias voltage signal may be equal to, greater than, or less than the second bias voltage signal. By independently optimizing the trigger levels of the substrate and gate of the transistor in the clamping circuit, a robust ESD protection circuit can be obtained to suit the requirements of different process technologies.

摘要翻译： 一种集成电路，包括信号焊盘，包括具有漏极，源极，栅极和衬底的第一NMOS晶体管的钳位电路，其中所述第一NMOS晶体管的漏极耦合到所述信号焊盘和所述第一NMOS晶体管的源极 NMOS晶体管耦合到地，以及耦合到第一NMOS晶体管和信号焊盘的栅极和衬底的控制电路，控制电路向栅极提供第一偏置电压信号和向衬底提供第二偏置电压信号。 第一偏置电压信号的电压电平可以等于，大于或小于第二偏置电压信号。 通过独立优化钳位电路中晶体管的基极和栅极的触发电平，可以获得强大的ESD保护电路，以适应不同工艺技术的要求。

公开(公告)号：US06717238B2

公开(公告)日：2004-04-06

申请号：US09818449

申请日：2001-03-27

申请人： Ming-Dou Ker ,  Hsin-Chin Jiang

发明人： Ming-Dou Ker ,  Hsin-Chin Jiang

IPC分类号： H01L2993

CPC分类号： H01L24/05 ,  H01L23/5222 ,  H01L24/48 ,  H01L2224/02122 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05012 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05567 ,  H01L2224/05599 ,  H01L2224/48463 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2224/45099 ,  H01L2924/00

摘要： A low-capacitance bonding pad for a semiconductor device. A diffusion region is formed in a substrate, and a bonding pad is formed on the substrate and aligned with the diffusion region. The bonding pad is made from a stacked metal layer and a metal layer. The stacked metal layer is made from a plurality of metal layers and a plurality of dielectric layers, and the metal layers and the dielectric layers are stacked alternately. The metal layers stacked in the stacked metal layer are formed with small areas. Each of the metal layers stacked in the stacked metal layer is coupled with the adjacent metal layer by via plugs.

摘要翻译： 一种用于半导体器件的低电容焊盘。 在衬底中形成扩散区，并且在衬底上形成接合焊盘并与扩散区对准。 接合焊盘由堆叠的金属层和金属层制成。 堆叠的金属层由多个金属层和多个电介质层制成，并且金属层和电介质层交替堆叠。 堆叠在层叠金属层中的金属层形成有小面积。 堆叠在堆叠金属层中的每个金属层通过插塞与相邻的金属层耦合。

公开(公告)号：US06690067B2

公开(公告)日：2004-02-10

申请号：US10330137

申请日：2002-12-30

申请人： Ming-Dou Ker ,  Che-Hao Chuang ,  Hsin-Chin Jiang

发明人： Ming-Dou Ker ,  Che-Hao Chuang ,  Hsin-Chin Jiang

IPC分类号： H01L2362

CPC分类号： H01L27/0259 ,  H01L27/0266 ,  H01L29/4238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A substrate-triggered ESD protection component having dummy gate structures. The ESD protection component includes a bipolar junction transistor (BJT), a substrate-triggering region to provide triggering current and a dummy gate structure. The BJT comprises a collector. The dummy gate structure has a poly-silicon gate adjacent to the collector and the substrate-triggering region. The emitter of the BJT is coupled to a power line, the collector is coupled to a pad, and the substrate-triggering region is coupled to an ESD detection circuit. During normal circuit operations, a base of the BJT is coupled with the power line through the ESD detection circuit to keep the BJT off. When an ESD event occurs between the pad and the power line, a triggering current is provided to the substrate-triggering region by the ESD detection circuit to trigger on the BJT and release ESD current.

摘要翻译： 具有虚拟栅极结构的衬底触发ESD保护组件。 ESD保护组件包括双极结型晶体管（BJT），提供触发电流的基板触发区域和虚拟栅极结构。 BJT包括收集器。 虚拟栅极结构具有与集电极和基板触发区相邻的多晶硅栅极。 BJT的发射极耦合到电源线，集电极耦合到焊盘，并且衬底触发区域耦合到ESD检测电路。 在正常电路操作期间，BJT的基极通过ESD检测电路与电源线耦合，以保持BJT断开。 当焊盘和电源线之间发生ESD事件时，ESD检测电路将触发电流提供给基板触发区域，以触发BJT并释放ESD电流。

公开(公告)号：US08773826B2

公开(公告)日：2014-07-08

申请号：US13598194

申请日：2012-08-29

申请人： Federico Agustin Altolaguirre ,  Ming-Dou Ker ,  Ryan Hsin-Chin Jiang

发明人： Federico Agustin Altolaguirre ,  Ming-Dou Ker ,  Ryan Hsin-Chin Jiang

IPC分类号： H02H9/00

CPC分类号： H02H9/046 ,  H01L2924/0002 ,  H01L2924/00

摘要： A power-rail ESD clamp circuit with a silicon controlled rectifier and a control module is provided. The silicon controlled rectifier is connected to a high voltage level and a low voltage level for bearing a current flow. The control module is connected to the silicon controlled rectifier in parallel, and includes a PMOS, a NMOS, at least one output diode, a resistor and a conducting string. The silicon controlled rectifier is a P+ or N+ triggered silicon controlled rectifier. By employing the novel power-rail ESD clamp circuit, it is extraordinarily advantageous of reducing both a standby leakage current and layout area while implementation.

摘要翻译： 提供了具有可控硅整流器和控制模块的电力轨道ESD钳位电路。 可控硅整流器连接到高电压电平和低电压电平以承受电流。 控制模块并联连接到可控硅整流器，并且包括PMOS，NMOS，至少一个输出二极管，电阻器和导电串。 可控硅整流器是P +或N +触发的可控硅整流器。 通过采用新型的电源轨ESD钳位电路，在实现时减少备用漏电流和布局面积是非常有利的。