公开(公告)号：US20080316830A1

公开(公告)日：2008-12-25

申请号：US11767622

申请日：2007-06-25

申请人： Nian Yang ,  Fan Wan Lai ,  Aaron Lee

发明人： Nian Yang ,  Fan Wan Lai ,  Aaron Lee

IPC分类号： G11C7/00

CPC分类号： G11C16/30 ,  G11C16/10

摘要： Systems and methodologies are provided herein for increasing operation speed uniformity in a flash memory device. Due to the characteristics of a typical flash memory array, memory cells in a memory array may experience distributed substrate resistance that increases as the distance of the memory cell from an edge of the memory array increases. This difference in distributed substrate resistance can vary voltages supplied to different memory cells in the memory array depending on their location, which can in turn cause non-uniformity in the speed of high voltage operations on the memory array such as programming. The systems and methodologies provided herein reduce this non-uniformity in operation speed by providing compensated voltage levels to memory cells in a memory array based at least in part on the location of each respective memory cell. For example, a compensated operation voltage can be provided that is higher near the center of the memory array and lower near an edge of the memory array, thereby lessening the effect of distributed substrate resistance and providing increased operation speed uniformity throughout the memory array.

摘要翻译： 本文提供的系统和方法用于提高闪存设备中的操作速度均匀性。 由于典型的闪存阵列的特征，存储器阵列中的存储器单元可能经历分布式衬底电阻，随着存储器单元与存储器阵列的边缘的距离增加而增加。 分布式基板电阻的这种差异可以根据其位置改变提供给存储器阵列中的不同存储单元的电压，这进而导致存储器阵列上的高电压操作的速度（例如编程）的不一致。 本文提供的系统和方法通过至少部分地基于每个相应存储器单元的位置，通过向存储器阵列中的存储器单元提供补偿的电压电平来降低操作速度的不均匀性。 例如，可以提供补偿操作电压，其在存储器阵列的中心附近较高，并且在存储器阵列的边缘附近较低，从而减小分布式衬底电阻的影响并且提供整个存储器阵列中的增加的操作速度均匀性。

公开(公告)号：US20080151639A1

公开(公告)日：2008-06-26

申请号：US11613383

申请日：2006-12-20

申请人： Nian Yang ,  Yonggang Wu ,  Aaron Lee ,  Wei Daisy Cai

发明人： Nian Yang ,  Yonggang Wu ,  Aaron Lee ,  Wei Daisy Cai

IPC分类号： G11C16/32

CPC分类号： G11C16/12

摘要： A semiconductor memory device (104) selectably connectable to an external high voltage power supply (122) is provided. The semiconductor memory device (104) includes a switch (314), a detector (316) and a timing device (318). The switch (314) is connected to external voltage supply signals and selectably couples the external voltage supply signals to memory cells (305) of the semiconductor memory device (104) for memory operations thereof. The external voltage supply signals including a high voltage signal (412) provided from the external high voltage power supply (122) and an operational voltage signal Vcc (402). The detector (316) is connected to the external voltage supply signals for generating a timer activation signal (404) in response to detecting an operational voltage power-on period. The timing device (318) signals the switch (314) to decouple the high voltage signal (412) and the operational voltage signal (402) from the memory cells (305) in response to the timer activation signal (404) and to recouple the high voltage signal (412) and the operational voltage signal (402) to the memory cells (305) a time delay interval thereafter. The time delay interval is determined in response to the high voltage signal (412).

摘要翻译： 提供可选择地连接到外部高压电源（122）的半导体存储器件（104）。 半导体存储器件（104）包括开关（314），检测器（316）和定时装置（318）。 开关（314）连接到外部电压源信号，并且可选择地将外部电压供应信号耦合到半导体存储器件（104）的存储单元（305），用于存储器操作。 包括从外部高压电源（122）提供的高电压信号（412）的外部电压供给信号和操作电压信号Vcc（402）。 检测器（316）连接到外部电压源信号，以响应于检测到工作电压通电周期而产生定时器激活信号（404）。 定时装置（318）响应于定时器启动信号（404），向开关314通知高压信号412和操作电压信号402与存储单元305的耦合， 高电压信号（412）和操作电压信号（402）到其后的时间延迟区间。 响应于高电压信号确定时间延迟间隔（412）。

公开(公告)号：US20080144391A1

公开(公告)日：2008-06-19

申请号：US11639935

申请日：2006-12-15

申请人： Nian Yang ,  Yonggang Wu ,  Tien-Chun Yang

发明人： Nian Yang ,  Yonggang Wu ,  Tien-Chun Yang

IPC分类号： G11C16/10

CPC分类号： G11C16/3404 ,  G11C16/0475

摘要： One embodiment of the invention relates to a method for accessing a memory cell. In this method, at least one bit of the memory cell is erased. After erasing the at least one bit, a soft program operation is performed to bias the memory cell thereby improving the reliability of data stored in the memory cell.Other methods and systems are also disclosed.

摘要翻译： 本发明的一个实施例涉及访问存储器单元的方法。 在该方法中，擦除存储单元的至少一位。 在擦除至少一个位之后，执行软编程操作以偏置存储器单元，从而提高存储在存储单元中的数据的可靠性。 还公开了其它方法和系统。

公开(公告)号：US07352626B1

公开(公告)日：2008-04-01

申请号：US11212614

申请日：2005-08-29

申请人： Yonggang Wu ,  Guowei Wang ,  Nian Yang ,  Aaron Lee

发明人： Yonggang Wu ,  Guowei Wang ,  Nian Yang ,  Aaron Lee

IPC分类号： G11C11/34 ,  G11C7/00

CPC分类号： G11C5/14

摘要： A voltage regulator may include an operational-amplifier section, a capacitor connected to an output of the operational-amplifier section, and a switch configured to connect the capacitor to a voltage supply. The switch is configured to charge the capacitor before activating the operational-amplifier section. The capacitor is configured to store charge to supplement current being supplied from the operational-amplifier section. The voltage regulator may be used to supply power to non-volatile memory cells.

摘要翻译： 电压调节器可以包括运算放大器部分，连接到运算放大器部分的输出的电容器和被配置为将电容器连接到电压源的开关。 开关被配置为在激活运算放大器部分之前对电容器充电。 电容器被配置为存储电荷以补充从运算放大器部分提供的电流。 电压调节器可以用于向非易失性存储单元供电。

公开(公告)号：US20070284609A1

公开(公告)日：2007-12-13

申请号：US11423649

申请日：2006-06-12

申请人： Boon-Aik Ang ,  Nian Yang ,  Yonggang Wu

发明人： Boon-Aik Ang ,  Nian Yang ,  Yonggang Wu

IPC分类号： H01L29/74

CPC分类号： G11C16/30 ,  G11C5/145 ,  H02M3/07

摘要： A method and apparatus are provided for improved power conservation in a semiconductor device (100) which includes a high voltage generating circuit (200) such as a drain pump. The operation frequency of the drain pump (200) is controlled in response to the high voltage level detected at the output thereof. In addition, highly efficient operation of the drain pump (200) can be achieved by enabling and disabling the drain pump (200) in response to the high voltage level to provide an output signal at a relatively constant high voltage level. The drain pump (200) is enabled in response to a high voltage detector (202, 402, 502) detecting a high voltage level lower than a first predetermined voltage level and is disabled in response to detecting a voltage level higher than a second predetermined voltage level, the second predetermined voltage level being higher than the first predetermined voltage level.

摘要翻译： 提供了一种用于在包括诸如排水泵的高电压产生电路（200）的半导体器件（100）中改善功率节省的方法和装置。 排水泵（200）的运转频率根据其输出端检测到的高电压电平进行控制。 此外，可以通过响应于高电压电平启用和禁用排水泵（200）来实现排水泵（200）的高效率操作，以在相对恒定的高电压电平提供输出信号。 响应于检测到低于第一预定电压电平的高电压电平的高电压检测器（202,402,502）响应于检测到高于第二预定电压的电压电平而禁用排水泵（200） 电平，第二预定电压电平高于第一预定电压电平。

公开(公告)号：US20070037371A1

公开(公告)日：2007-02-15

申请号：US11201042

申请日：2005-08-10

申请人： Zhigang Wang ,  Nian Yang ,  Shenqing Fang

发明人： Zhigang Wang ,  Nian Yang ,  Shenqing Fang

IPC分类号： H01L21/3205

CPC分类号： H01L21/32139 ,  H01L21/28123

摘要： In one example, the method includes forming a patterned hard mask feature above a layer of gate electrode material, the hard mask feature having a photoresist feature formed thereabove and the hard mask feature having a critical dimension. The method further includes performing an etching process on the patterned hard mask feature to produce a reduced hard mask feature having a critical dimension that is less than the critical dimension of the patterned hard mask feature and performing an anisotropic etching process on the layer of gate electrode material using the reduced hard mask feature as a mask to define a gate electrode.

摘要翻译： 在一个示例中，该方法包括在栅电极材料层之上形成图案化的硬掩模特征，硬掩模特征具有形成在其上的光致抗蚀剂特征以及具有临界尺寸的硬掩模特征。 该方法还包括对图案化的硬掩模特征进行蚀刻处理以产生具有小于图案化硬掩模特征的临界尺寸的临界尺寸并且在栅电极层上执行各向异性蚀刻工艺的减小的硬掩模特征 使用减少的硬掩模特征作为掩模的材料来限定栅电极。

公开(公告)号：US06991987B1

公开(公告)日：2006-01-31

申请号：US10306382

申请日：2002-11-27

申请人： Xin Guo ,  Nian Yang ,  Zhigang Wang

发明人： Xin Guo ,  Nian Yang ,  Zhigang Wang

IPC分类号： H01L21/8247

CPC分类号： H01L21/28273 ,  C23C16/0218 ,  C23C16/0227 ,  C23C16/308 ,  H01L21/3144

摘要： A process technology effectuates production of low defect homogeneous oxynitride, which can be applied in tunneling dielectrics with high dielectric constants and low barrier heights for flash memory devices, and as gate oxide for ultra-thin logic devices. The process technology involves varying the oxygen content in a the homogeneous oxynitride film comprising a part of the flash memory device, which effectively increases the dielectric constant of the oxynitride film and lowers its barrier height. In one such process, a controlled co-flow of N2O is introduced into a CVD deposition process. This process effectuates production of a oxynitride film with uniform distributions of nitrogen and oxygen throughout.

摘要翻译： 一种工艺技术可以实现低缺陷均匀氮氧化物的生产，其可以应用于具有高介电常数的隧道电介质和用于闪存器件的低屏障高度，以及用作超薄逻辑器件的栅极氧化物。 该工艺技术涉及改变包括闪存器件的一部分的均匀氮氧化物膜中的氧含量，其有效地增加氧氮化物膜的介电常数并降低其势垒高度。 在一种这样的方法中，将N 2 O 2的受控共流引入到CVD沉积工艺中。 该方法实现了氮气和氧气的均匀分布的氮氧化物膜的生产。

公开(公告)号：US20060007752A1

公开(公告)日：2006-01-12

申请号：US10885268

申请日：2004-07-06

申请人： Zhigang Wang ,  Nian Yang ,  Shenqing Fang

发明人： Zhigang Wang ,  Nian Yang ,  Shenqing Fang

IPC分类号： G11C11/34

CPC分类号： G11C16/16 ,  G11C16/0491 ,  H01L27/115

摘要： Techniques for erasing memory devices of a flash memory array having a plurality of operative wordlines and at least one dummy wordline adjacent an end one of the operative wordlines are disclosed. Erasing the memory devices can include applying a gate voltage to the wordlines and applying a bias voltage to the dummy wordlines. In one arrangement, an electrical connection is established between the dummy wordline and the end one of the operative wordlines.

摘要翻译： 公开了一种用于擦除具有多个操作字线的闪速存储器阵列的存储器件以及与操作字线的末端相邻的至少一个伪字线的技术。 擦除存储器件可以包括将栅极电压施加到字线并将偏置电压施加到伪字线。 在一种布置中，在伪字线和操作字线的末端之间建立电连接。

公开(公告)号：US06825526B1

公开(公告)日：2004-11-30

申请号：US10759809

申请日：2004-01-16

申请人： Yue-Song He ,  Nian Yang ,  Zhigang Wang

发明人： Yue-Song He ,  Nian Yang ,  Zhigang Wang

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： According to one exemplary embodiment, a memory array comprises first and second isolation regions situated in a substrate, where the first and second isolation regions are separated by a separation distance. The memory array further comprises a trench situated between the first and second isolation regions, where the trench defines trench sidewalls and a trench bottom in the substrate. The memory array further comprises a tunnel oxide layer situated between the first and second isolation regions, where the tunnel oxide layer is situated on the trench sidewalls and the trench bottom. According to this embodiment, the memory array further comprises a channel region situated underneath the tunnel oxide layer and extending along the trench sidewalls and the trench bottom, where the channel region has an effective channel width, where the effective channel width increases as a height of the trench sidewalls increases.

摘要翻译： 根据一个示例性实施例，存储器阵列包括位于衬底中的第一和第二隔离区域，其中第一和第二隔离区域被分离距离。 存储器阵列还包括位于第一和第二隔离区之间的沟槽，其中沟槽限定衬底中的沟槽侧壁和沟底。 存储器阵列还包括位于第一和第二隔离区之间的隧道氧化物层，其中隧道氧化物层位于沟槽侧壁和沟槽底部。 根据该实施例，存储器阵列还包括位于隧道氧化物层下方并沿着沟槽侧壁和沟槽底部延伸的沟道区，其中沟道区具有有效沟道宽度，其中有效沟道宽度随着 沟槽侧壁增加。

公开(公告)号：US06696331B1

公开(公告)日：2004-02-24

申请号：US10217807

申请日：2002-08-12

申请人： Nian Yang ,  Zhigang Wang ,  Hsiao-Han Thio

发明人： Nian Yang ,  Zhigang Wang ,  Hsiao-Han Thio

IPC分类号： H01L218238

CPC分类号： H01L21/28273 ,  H01L29/42324

摘要： A method of protecting a stacked gate structure of a flash memory device during fabrication is disclosed. Additionally, the manner of protecting the stacked gate structure during fabrication is simple to implement and is cost-effective. In particular, a protective layer is deposited on the stacked gate structure to protect the stacked gate structure before a resist removal process is performed a second time. Despite undergoing two resist removal processes, the stacked gate structure suffers less damage than the convention fabrication techniques, increasing the yield and reliability of the flash memory device.

摘要翻译： 公开了一种在制造期间保护闪存器件的堆叠栅极结构的方法。 此外，在制造期间保护堆叠栅极结构的方式易于实现并且是成本有效的。 特别地，在堆叠的栅极结构上沉积保护层，以在第二次执行抗蚀剂去除处理之前保护堆叠的栅极结构。 尽管经历了两次抗蚀剂去除工艺，堆叠的栅极结构比常规的制造技术遭受的损坏更小，从而提高了闪存器件的产量和可靠性。