公开(公告)号：US08772127B2

公开(公告)日：2014-07-08

申请号：US13142591

申请日：2011-01-27

申请人： Haizhou Yin ,  Huicai Zhong ,  Huilong Zhu ,  Zhijiong Luo

发明人： Haizhou Yin ,  Huicai Zhong ,  Huilong Zhu ,  Zhijiong Luo

IPC分类号： H01L29/772

CPC分类号： H01L29/7846 ,  H01L21/76224 ,  H01L29/045 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention provides a semiconductor device and a method for manufacturing the same. The method for manufacturing the semiconductor device comprises: providing a silicon substrate having a gate stack structure formed thereon and having {100} crystal indices; forming an interlayer dielectric layer coving a top surface of the silicon substrate; forming a first trench in the interlayer dielectric layer and/or in the gate stack structure, the first trench having an extension direction being along crystal direction and perpendicular to that of the gate stack structure; and filling the first trench with a first dielectric layer, wherein the first dielectric layer is a tensile stress dielectric layer. The present invention introduces a tensile stress in the transverse direction of a channel region by using a simple process, which improves the response speed and performance of semiconductor devices.

摘要翻译： 本发明提供一种半导体器件及其制造方法。 制造半导体器件的方法包括：提供其上形成有栅极叠层结构并具有{100}晶体指数的硅衬底; 形成层叠所述硅衬底的顶表面的层间电介质层; 在所述层间介质层和/或所述栅堆叠结构中形成第一沟槽，所述第一沟槽具有沿着晶体方向并且垂直于所述栅堆叠结构的延伸方向; 以及用第一介电层填充所述第一沟槽，其中所述第一介电层是拉伸应力介电层。 本发明通过使用简单的工艺在沟道区域的横向上引入拉伸应力，这提高了半导体器件的响应速度和性能。

公开(公告)号：US20120187501A1

公开(公告)日：2012-07-26

申请号：US13379407

申请日：2011-05-11

申请人： Huilong Zhu ,  Huicai Zhong ,  Haizhou Yin ,  Zhijiong Luo

发明人： Huilong Zhu ,  Huicai Zhong ,  Haizhou Yin ,  Zhijiong Luo

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/3086 ,  H01L21/76224 ,  H01L21/76229 ,  H01L29/66636 ,  H01L29/7848

摘要： The present application discloses a semiconductor structure and a method for manufacturing the same. Compared with conventional approaches to form contacts, the present disclosure reduces contact resistance and avoids a short circuit between a gate and contact plugs, while simplifying manufacturing process, increasing integration density, and lowering manufacture cost. According to the manufacturing method of the present disclosure, second shallow trench isolations are formed with an upper surface higher than an upper surface of the source/drain regions. Regions defined by sidewall spacers of the gate, sidewall spacers of the second shallow trench isolations, and the upper surface of the source/drain regions are formed as contact holes. The contacts are formed by filling the contact holes with a conductive material. The method omits the steps of etching for providing the contact holes, which lowers manufacture cost. By forming the contacts self-aligned with the gate, the method avoids misalignment and improves performance of the device while reducing a footprint of the device and lowering manufacture cost of the device.

摘要翻译： 本申请公开了一种半导体结构及其制造方法。 与传统的形成触点的方法相比，本公开减少了接触电阻，并且避免了栅极和接触插塞之间的短路，同时简化了制造工艺，增加了集成密度并降低了制造成本。 根据本公开的制造方法，形成第二浅沟槽隔离件，其上表面高于源极/漏极区域的上表面。 由栅极的侧壁间隔物，第二浅沟槽隔离件的侧壁间隔件和源极/漏极区域的上表面限定的区域形成为接触孔。 通过用导电材料填充接触孔来形成触点。 该方法省略了用于提供接触孔的蚀刻步骤，这降低了制造成本。 通过形成与栅极自对准的触点，该方法避免了未对准并且提高了器件的性能，同时减少了器件的占地面积并降低了器件的制造成本。

公开(公告)号：US20120112288A1

公开(公告)日：2012-05-10

申请号：US13142378

申请日：2011-03-02

申请人： Zhijiong Luo ,  Haizhou Yin ,  Huilong Zhu ,  Huicai Zhong

发明人： Zhijiong Luo ,  Haizhou Yin ,  Huilong Zhu ,  Huicai Zhong

IPC分类号： H01L27/04 ,  H01L21/762

CPC分类号： H01L21/76232 ,  H01L21/823481

摘要： The present invention provides an isolation structure for a semiconductor substrate and a method for manufacturing the same, as well as a semiconductor device having the structure. The present invention relates to the field of semiconductor manufacture. The isolation structure comprises: a trench embedded in a semiconductor substrate; an oxide layer covering the bottom and sidewalls of the trench, and isolation material in the trench and on the oxide layer, wherein a portion of the oxide layer on an upper portion of the sidewalls of the trench comprises lanthanum-rich oxide. By the trench isolation structure according to the present invention, metal lanthanum in the lanthanum-rich oxide can diffuse into corners of the oxide layer of the gate stack, thus alleviating the impact of the narrow channel effect and making the threshold voltage adjustable.

摘要翻译： 本发明提供一种用于半导体衬底的隔离结构及其制造方法，以及具有该结构的半导体器件。 本发明涉及半导体制造领域。 隔离结构包括：嵌入在半导体衬底中的沟槽; 覆盖沟槽的底部和侧壁的氧化物层，以及沟槽和氧化物层上的隔离材料，其中沟槽侧壁上部的氧化物层的一部分包括富镧氧化物。 通过根据本发明的沟槽隔离结构，富镧氧化物中的金属镧可以扩散到栅极堆叠的氧化物层的角部，从而减轻窄沟道效应的影响并使阈值电压可调。

公开(公告)号：US20150295067A1

公开(公告)日：2015-10-15

申请号：US14004802

申请日：2012-12-07

申请人： Qiuxia Xu ,  Huilong Zhu ,  Huajie Zhou ,  Gaobo Xu ,  Qingqing Liang

发明人： Qiuxia Xu ,  Huilong Zhu ,  Huajie Zhou ,  Gaobo Xu ,  Qingqing Liang

IPC分类号： H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51 ,  H01L21/02 ,  H01L21/265 ,  H01L29/49

CPC分类号： H01L29/66545 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/265 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/3215 ,  H01L29/42364 ,  H01L29/49 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7833

摘要： The present disclosure discloses a method for manufacturing a P-type MOSFET, comprising: forming a part of the MOSFET on a semiconductor substrate, the part of the MOSFET comprising source/drain regions in the semiconductor substrate, a replacement gate stack between the source/drain regions above the semiconductor substrate, and a gate spacer surrounding the replacement gate stack; removing the replacement gate stack of the MOSFET to form a gate opening exposing a surface of the semiconductor substrate; forming an interface oxide layer on the exposed surface of the semiconductor; forming a high-K gate dielectric layer on the interface oxide layer in the gate opening; forming a first metal gate layer on the high-K gate dielectric layer; implanting dopant ions into the first metal gate layer; and performing annealing to cause the dopant ions to diffuse and accumulate at an upper interface between the high-K gate dielectric layer and the first metal gate layer and a lower interface between the high-K gate dielectric layer and the interface oxide layer, and also to generate electric dipoles by interfacial reaction at the lower interface between the high-K gate dielectric layer and the interface oxide layer.

摘要翻译： 本公开公开了一种用于制造P型MOSFET的方法，包括：在半导体衬底上形成MOSFET的一部分，所述MOSFET的部分包括半导体衬底中的源/漏区，源极/ 在半导体衬底之上的漏极区域和围绕替换栅极堆叠的栅极间隔; 去除MOSFET的替换栅极堆叠以形成暴露半导体衬底的表面的栅极开口; 在所述半导体的暴露表面上形成界面氧化物层; 在栅极开口中的界面氧化物层上形成高K栅极电介质层; 在高K栅极电介质层上形成第一金属栅极层; 将掺杂剂离子注入到第一金属栅极层中; 并且进行退火以使掺杂剂离子在高K栅极介电层和第一金属栅极层之间的上部界面以及高K栅极介电层和界面氧化物层之间的下部界面处扩散和积聚，并且还 通过界面反应在高K栅极介电层和界面氧化物层之间的下界面产生电偶极子。

公开(公告)号：US08816392B2

公开(公告)日：2014-08-26

申请号：US13121998

申请日：2011-03-02

申请人： Huilong Zhu ,  Qingqing Liang

发明人： Huilong Zhu ,  Qingqing Liang

IPC分类号： H01L29/66 ,  H01L33/00 ,  H01L21/02

CPC分类号： H01L29/66 ,  B82Y10/00 ,  H01L21/02 ,  H01L21/28273 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/66825 ,  H01L29/785 ,  H01L33/00

摘要： A semiconductor device comprises a semiconductor substrate on an insulating layer; and a second gate that is located on the insulating layer and is embedded at least partially in the semiconductor substrate. A method for forming a semiconductor device comprises: forming a semiconductor substrate on an insulating layer; forming a void within the semiconductor substrate, with the insulating layer being exposed by the void; and forming a second gate, with the void being filled with at least one part of the second gate. It facilitates the reduction of the short channel effects, resistances of the source and drain regions, and parasitic capacitances.

摘要翻译： 半导体器件包括绝缘层上的半导体衬底; 以及第二栅极，其位于所述绝缘层上并且至少部分地嵌入所述半导体衬底中。 一种形成半导体器件的方法包括：在绝缘层上形成半导体衬底; 在半导体衬底内形成空隙，绝缘层被空隙暴露; 以及形成第二栅极，其中空隙填充有第二栅极的至少一部分。 它有助于减少短沟道效应，源极和漏极区域的电阻以及寄生电容。

公开(公告)号：US08815660B2

公开(公告)日：2014-08-26

申请号：US12700797

申请日：2010-02-05

申请人： Qingqing Liang ,  Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin

发明人： Qingqing Liang ,  Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin

IPC分类号： H01L29/786

CPC分类号： H01L27/1203 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0688 ,  H01L29/6675 ,  H01L29/78615 ,  H01L29/78624 ,  H01L29/78687

摘要： The present invention generally relates to a semiconductor structure and method, and more specifically, to a structure and method for reducing floating body effect of silicon on insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs). An integrated circuit (IC) structure includes a SOI substrate and at least one MOSFET formed on the SOI substrate. Additionally, the IC structure includes an asymmetrical source-drain junction in the at least one MOSFET by damaging a pn junction to reduce floating body effects of the at least one MOSFET.

摘要翻译： 本发明一般涉及半导体结构和方法，更具体地说，涉及用于减少绝缘体上硅（SOI）金属氧化物半导体场效应晶体管（MOSFET）的浮体效应的结构和方法。 集成电路（IC）结构包括SOI衬底和形成在SOI衬底上的至少一个MOSFET。 此外，IC结构包括通过损坏pn结在至少一个MOSFET中的不对称源极 - 漏极结，以减少至少一个MOSFET的浮体效应。

公开(公告)号：US08716799B2

公开(公告)日：2014-05-06

申请号：US13376996

申请日：2011-08-01

申请人： Huilong Zhu ,  Miao Xu ,  Qingqing Liang

发明人： Huilong Zhu ,  Miao Xu ,  Qingqing Liang

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L29/78648 ,  H01L21/2652

摘要： The present application discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer, which comprises a semiconductor substrate, a buried insulator layer, and a semiconductor layer, the buried insulator layer being disposed on the semiconductor substrate, and the semiconductor layer being disposed on the buried insulator layer; a gate stack, which is disposed on the semiconductor layer; a source region and a drain region, which are disposed in the semiconductor layer and on opposite sides of the gate stack; and a channel region, which are disposed in the semiconductor layer and sandwiched by the source region and the drain region, wherein the MOSFET further comprises a back gate disposed in the semiconductor substrate, and wherein the back gate comprises first, second and third compensation doping regions, the first compensation doping region is disposed under the source region and the drain region; the second compensation doping region extends in a direction away from the channel region and adjoining the first compensation doping region; and the third compensation doping region is disposed under the channel region and adjoining the first compensation doping region. By changing the doping type of the back gate, the MOSFET can have an adjustable threshold voltage, and can have a reduced parasitic capacitance and a reduced contact resistance in connection with the back gate.

摘要翻译： 本申请公开了一种MOSFET及其制造方法，其中，所述MOSFET包括：SOI晶片，其包含半导体基板，埋入绝缘体层和半导体层，所述埋入绝缘体层设置在所述半导体基板上， 并且所述半导体层设置在所述埋入绝缘体层上; 栅极堆叠，其设置在半导体层上; 源极区域和漏极区域，其设置在所述半导体层中并且在所述栅极堆叠的相对侧上; 以及沟道区域，其设置在所述半导体层中并且被所述源极区域和所述漏极区域夹持，其中所述MOSFET还包括设置在所述半导体衬底中的背栅极，并且其中所述后栅极包括第一，第二和第三补偿掺杂 第一补偿掺杂区域设置在源极区域和漏极区域下方; 所述第二补偿掺杂区域在远离所述沟道区域并邻接所述第一补偿掺杂区域的方向上延伸; 并且第三补偿掺杂区域设置在沟道区域的下方并与第一补偿掺杂区域相邻。 通过改变背栅的掺杂类型，MOSFET可以具有可调的阈值电压，并且可以具有减小的寄生电容和与后栅极相关联的降低的接触电阻。

公开(公告)号：US08367490B2

公开(公告)日：2013-02-05

申请号：US13144182

申请日：2011-03-04

申请人： Huilong Zhu ,  Qingqing Liang ,  Haizhou Yin ,  Zhijiong Luo

发明人： Huilong Zhu ,  Qingqing Liang ,  Haizhou Yin ,  Zhijiong Luo

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L21/84 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/6675 ,  H01L29/78603 ,  H01L29/78648 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present application discloses a semiconductor structure and a method for manufacturing the same. The semiconductor structure according to the present invention adjusts a threshold voltage with a common contact, which has a portion outside the source or drain region extending to the back-gate region and provides an electrical contact of the source or drain region and the back-gate region, which leads to a simple manufacturing process, an increased integration level and a lowered manufacture cost. Moreover, the asymmetric design of the back-gate structure further increases the threshold voltage and improves the performance of the device.

摘要翻译： 本申请公开了一种半导体结构及其制造方法。 根据本发明的半导体结构利用公共接触来调节阈值电压，该公共触点具有延伸到背栅极区域的源极或漏极区域之外的部分并且提供源极或漏极区域与背栅极的电接触 区域，这导致简单的制造过程，增加的集成水平和降低的制造成本。 此外，背栅结构的非对称设计进一步增加了阈值电压并提高了器件的性能。

公开(公告)号：US20120187491A1

公开(公告)日：2012-07-26

申请号：US13429948

申请日：2012-03-26

申请人： Huilong Zhu ,  Zhijiong Luo ,  Qingqing Liang ,  Haizhou Yin

发明人： Huilong Zhu ,  Zhijiong Luo ,  Qingqing Liang ,  Haizhou Yin

IPC分类号： H01L29/772

CPC分类号： H01L21/187 ,  H01L21/6835 ,  H01L21/84 ,  H01L27/12 ,  H01L29/1083 ,  H01L2221/6835 ,  H01L2221/68368

摘要： A method of forming an electrical device is provided that includes forming at least one semiconductor device on a first semiconductor layer of the SOI substrate. A handling structure is formed contacting the at least one semiconductor device and the first semiconductor layer. A second semiconductor layer and at least a portion of the dielectric layer of the SOI substrate are removed to provide a substantially exposed surface of the first semiconductor layer. A retrograded well may be formed by implanting dopant through the substantially exposed surface of the first semiconductor layer into a first thickness of the semiconductor layer that extends from the substantially exposed surface of the semiconductor layer, wherein a remaining thickness of the semiconductor layer is substantially free of the retrograded well dopant. The retrograded well may be laser annealed.

摘要翻译： 提供一种形成电气装置的方法，包括在SOI衬底的第一半导体层上形成至少一个半导体器件。 形成接触至少一个半导体器件和第一半导体层的处理结构。 去除第二半导体层和SOI衬底的电介质层的至少一部分以提供第一半导体层的基本暴露的表面。 可以通过将掺杂剂通过第一半导体层的基本上暴露的表面注入从半导体层的基本暴露的表面延伸的半导体层的第一厚度来形成退化的阱，其中半导体层的剩余厚度基本上不含 的回归井掺杂剂。 退火井可以进行激光退火。

公开(公告)号：US20120146103A1

公开(公告)日：2012-06-14

申请号：US13378206

申请日：2011-02-27

申请人： Huilong Zhu ,  Qingqing Liang ,  Haizhou Yin ,  Zhijiong Luo

发明人： Huilong Zhu ,  Qingqing Liang ,  Haizhou Yin ,  Zhijiong Luo

IPC分类号： H01L27/092 ,  H01L21/336

CPC分类号： H01L29/165 ,  H01L21/30608 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66583 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7834 ,  H01L29/7849

摘要： The present application discloses a semiconductor device and a method of manufacturing the same. Wherein, the semiconductor device comprises: a semiconductor substrate; a stressor embedded in the semiconductor substrate; a channel region disposed on the stressor; a gate stack disposed on the channel region; a source/drain region disposed on two sides of the channel region and embedded in the semiconductor substrate; wherein, surfaces of the stressor comprise a top wall, a bottom wall, and side walls, the side walls comprising a first side wall and a second side wall, the first side wall connecting the top wall and the second side wall, the second side wall connecting the first side wall and the bottom wall, the angle between the first side wall and the second side wall being less than 180°, and the first sidewall and the second side wall being roughly symmetrical with respect to a plane parallel to the semiconductor substrate. Embodiments of the present invention are applicable to the stress engineering technology in the semiconductor device manufacturing.

摘要翻译： 本申请公开了半导体器件及其制造方法。 其中，所述半导体器件包括：半导体衬底; 嵌入在半导体衬底中的应力器; 设置在所述应力器上的通道区域; 设置在通道区域上的栅极堆叠; 源极/漏极区域，设置在沟道区域的两侧并且嵌入在半导体衬底中; 其中，所述应力器的表面包括顶壁，底壁和侧壁，所述侧壁包括第一侧壁和第二侧壁，所述第一侧壁连接所述顶壁和所述第二侧壁，所述第二侧 连接第一侧壁和底壁的壁，第一侧壁和第二侧壁之间的角度小于180°，第一侧壁和第二侧壁相对于平行于半导体的平面大致对称 基质。 本发明的实施例可应用于半导体器件制造中的应力工程技术。