公开(公告)号：US20080115019A1

公开(公告)日：2008-05-15

申请号：US11559436

申请日：2006-11-14

申请人： Hung C. Ngo ,  Gary D. Carpenter ,  Alan J. Drake ,  Jente B. Kuang

发明人： Hung C. Ngo ,  Gary D. Carpenter ,  Alan J. Drake ,  Jente B. Kuang

IPC分类号： G01R31/28

CPC分类号： G01R31/31727 ,  G01R31/31725 ,  G01R31/31726

摘要： An in-circuit timing monitor having a selectable-path ring oscillator circuit provides delay and performance measurements in an actual circuit environment. A test mode signal is applied to a digital circuit to de-select a given functional input signal applied to a functional logic block within the digital circuit and replace it with feedback coupled from an output of the functional logic block, when test mode operation is selected. The signal path from the de-selected input to the output is selected so that the signal path will oscillate, and a characteristic frequency or phase of the output signal is measured to determine the delay. Other inputs to the functional logic block are set to a predetermined set of logic values. The selection may be made at a register preceding the digital inputs or made in the first level of logic of the functional logic block.

摘要翻译： 具有可选路径环形振荡器电路的在线定时监视器在实际电路环境中提供延迟和性能测量。 测试模式信号被施加到数字电路以取消选择施加到数字电路内的功能逻辑块的给定功能输入信号，并且当选择测试模式操作时，将其与从功能逻辑块的输出耦合的反馈替换 。 选择从选择输入到输出的信号路径，使得信号路径振荡，并且测量输出信号的特征频率或相位以确定延迟。 将功能逻辑块的其他输入设置为预定的一组逻辑值。 可以在数字输入之前的寄存器处进行选择，或者在功能逻辑块的逻辑的第一级中进行选择。

公开(公告)号：US07323908B2

公开(公告)日：2008-01-29

申请号：US11260571

申请日：2005-10-27

申请人： Ching-Te Chuang ,  Jente B. Kuang ,  Hung C. Ngo

发明人： Ching-Te Chuang ,  Jente B. Kuang ,  Hung C. Ngo

IPC分类号： H03K19/0175 ,  H03K19/094 ,  H03K3/03

CPC分类号： G01R31/31725

摘要： A cascaded pass-gate test circuit including interposed split-output drive devices provides accurate measurement of critical timing parameters of pass gates. The rise time and fall time of signals passed through the pass gate can be separately measured in a ring oscillator or one-shot delay line configuration. Inverters or other buffer circuits are provided as drive devices to couple the pass gates in cascade. The final complementary tree in each drive device is split so that the only one of the output pull-down transistor or pull-up transistor is connected to the next pass gate input, while the other transistor is connected to the output of the pass gate. The result is that the state transition associated with the device connected to the pass gate input is dominant in the delay, while the other state transition is propagated directly to the output of the pass gate, bypassing the pass gate.

摘要翻译： 包括插入式分离输出驱动装置的级联通过栅极测试电路提供对通孔的临界定时参数的精确测量。 通过通过门的信号的上升时间和下降时间可以在环形振荡器或单稳态延迟线配置中单独测量。 逆变器或其它缓冲电路被提供作为驱动装置来串联耦合通过门。 每个驱动装置中的最终互补树被分开，使得输出下拉晶体管或上拉晶体管中的唯一一个连接到下一个通过栅极输入，而另一个晶体管连接到通过栅极的输出端。 结果是，与连接到通过栅极输入的器件相关联的状态转变在延迟中是主要的，而另一个状态转变直接传播到通过栅极的输出，绕过通过栅极。

公开(公告)号：US07298176B2

公开(公告)日：2007-11-20

申请号：US11204401

申请日：2005-08-16

申请人： Hung C. Ngo ,  Ching-Te Chuang ,  Keunwoo Kim ,  Jente B. Kuang ,  Kevin J. Nowka

发明人： Hung C. Ngo ,  Ching-Te Chuang ,  Keunwoo Kim ,  Jente B. Kuang ,  Kevin J. Nowka

IPC分类号： H03K19/20

CPC分类号： H03K19/0963

摘要： A dynamic logic gate has an asymmetrical dual-gate PFET device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node during an evaluate phase of the clock. The front gate of the asymmetrical dual-gate PFET device is coupled to the clock signal and the back gate is coupled to the ground potential of the power supply. When the clock is a logic zero both the front gate and the back gate are biased ON and the dynamic node charges with maximum current. The clock signal transitions to a logic one during the evaluation phase of the clock turning OFF the front gate. The back gate remains ON and the asymmetrical dual-gate PFET device operates as a keeper device with a current level sufficient to counter leakage on the dynamic node.

摘要翻译： 动态逻辑门具有非对称双栅极PFET器件，用于在时钟的预充电阶段期间对动态节点进行充电。 逻辑树在时钟的评估阶段评估动态节点。 非对称双栅极PFET器件的前栅极耦合到时钟信号，而后栅极耦合到电源的地电位。 当时钟为逻辑0时，前门和后门都被偏置为ON，动态节点以最大电流充电。 在时钟关断前门的评估阶段，时钟信号转变为逻辑1。 背栅保持接通，并且非对称双栅极PFET器件作为具有足以抵抗动态节点上的泄漏的电流水平的保持器器件工作。

公开(公告)号：US07288975B2

公开(公告)日：2007-10-30

申请号：US11260563

申请日：2005-10-27

申请人： Hung C. Ngo ,  Gary D. Carpenter ,  Fadi H. Gebara ,  Jente B. Kuang

发明人： Hung C. Ngo ,  Gary D. Carpenter ,  Fadi H. Gebara ,  Jente B. Kuang

IPC分类号： H03L7/06

CPC分类号： H03L7/18 ,  G06F1/04

摘要： A method and apparatus for fail-safe and restartable system clock generation provides recovery from failures due to incorrect clock generator settings or from marginal clock distribution components. Clock failure is detected at a point along the clock distribution path between the output of the clock generator and the downstream circuits. If a clock failure is detected, a second clock, which may be the clock generator reference clock, is used to operate the downstream circuits. The clock generator, which may be a phase-lock loop, is then restarted, either with a predetermined loop filter voltage at which downstream circuits are guaranteed to operate, or with a divider setting on the output of the clock generator that reduces the frequency so that downstream circuits are guaranteed to operate. Parameters of the clock generator can thereby be reset and operating conditions determined before restoring the output of the clock generator to the downstream circuits.

公开(公告)号：US06177708B1

公开(公告)日：2001-01-23

申请号：US09324324

申请日：1999-06-02

申请人： Jente B. Kuang ,  John P. Pennings ,  George E. Smith, III ,  Michael H. Wood

发明人： Jente B. Kuang ,  John P. Pennings ,  George E. Smith, III ,  Michael H. Wood

IPC分类号： H01L2941

CPC分类号： H01L27/1203 ,  H01L29/42384 ,  H01L29/78606 ,  H01L29/78618

摘要： A self-aligned SOI FET device with an “L” shaped gate structure allows an integral diode junction to be formed between the source and the body of the device. Two devices with this gate geometry can be advantageously placed side-by-side in a single rx opening that could accommodate but a single device with a “T” shaped gate structure. The devices in accordance with the teachings of this invention can be easily formed using standard prior art SOI processing steps. An aspect of this invention includes the use of these novel SOI devices with their body and source connected together in circuit applications, such as memory cell sense amplifiers, where high speed operation commends the use of SOI technology, but physical space considerations have limited their application.

摘要翻译： 具有“L”形栅极结构的自对准SOI FET器件允许在器件的源极和主体之间形成整体二极管结。 具有该栅极几何形状的两个器件可以有利地并排布置在可容纳但具有“T”形栅极结构的单个器件的单个rx开口中。 根据本发明的教导的器件可以使用标准的现有技术的SOI处理步骤容易地形成。 本发明的一个方面包括使用这些新颖的SOI器件，其主体和源极在诸如存储器单元读出放大器的电路应用中连接在一起，其中高速操作表示使用SOI技术，但是物理空间考虑限制了它们的应用 。

公开(公告)号：US6078058A

公开(公告)日：2000-06-20

申请号：US35407

申请日：1998-03-05

申请人： Louis L. Hsu ,  Jente B. Kuang ,  Somnuk Ratanaphanyarat ,  Mary J. Saccamango

发明人： Louis L. Hsu ,  Jente B. Kuang ,  Somnuk Ratanaphanyarat ,  Mary J. Saccamango

IPC分类号： H02H9/04 ,  H01L23/58 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H02H9/046

摘要： Apparatus and method for discharging the body of a monitored SOI device through first and second discharge circuits. The second discharge circuit is selectively activated when the body potential of the monitored SOI device is at a level such that the body charge of the monitored SOI device cannot be discharged entirely through the first discharge circuit within normal operating cycle time allowances.

摘要翻译： 通过第一和第二放电电路对被监测的SOI器件的体放电的装置和方法。 当所监视的SOI器件的体电位处于使得所监视的SOI器件的体电量在正常工作周期时间容限内不能通过第一放电电路完全放电的水平时，选择性地激活第二放电电路。

公开(公告)号：US5736891A

公开(公告)日：1998-04-07

申请号：US585336

申请日：1996-01-11

申请人： Taqi Nasser Buti ,  Louis Lu-Chen Hsu ,  Jente B. Kuang ,  Somnuk Ratanaphanyarat ,  Mary J. Saccamango ,  Hyun Jong Shin

发明人： Taqi Nasser Buti ,  Louis Lu-Chen Hsu ,  Jente B. Kuang ,  Somnuk Ratanaphanyarat ,  Mary J. Saccamango ,  Hyun Jong Shin

IPC分类号： G11C16/30 ,  H03K17/10 ,  H03K17/687

CPC分类号： H03K17/102 ,  G11C16/30 ,  H03K17/6872

摘要： A discharge circuit for a semiconductor memory includes a first node, a second node for receiving a control signal having first and second states, and a circuit connected between the first node and ground potential and to the second node. The circuit couples the first node to ground potential when the control signal has the first state and substantially isolates the first node from ground potential when the control signal has the second state. The circuit includes a first subcircuit for defining a current path between the first node and ground potential. The first subcircuit includes a plurality of transistors connected in series, each of which having a gate, source and drain. The circuit further includes a second subcircuit for effecting predetermined gate-to-source, and drain-to-source voltages of the transistors of the first subcircuit when the control signal has the second state.

摘要翻译： 用于半导体存储器的放电电路包括第一节点，用于接收具有第一和第二状态的控制信号的第二节点和连接在第一节点和地电位之间的电路以及连接到第二节点的电路。 当控制信号具有第一状态时，电路将第一节点耦合到地电位，并且当控制信号具有第二状态时，电路基本上将第一节点与地电势隔离。 电路包括用于限定第一节点和地电位之间的电流路径的第一子电路。 第一分支电路包括串联连接的多个晶体管，每个晶体管具有栅极，源极和漏极。 当控制信号具有第二状态时，电路还包括用于实现第一子电路的晶体管的预定栅极至源极和漏极至源极电压的第二子电路。