公开(公告)号：US06727995B1

公开(公告)日：2004-04-27

申请号：US09903884

申请日：2001-07-12

申请人： Arvind Halliyal ,  Bhanwar Singh ,  Ramkumar Subramanian

发明人： Arvind Halliyal ,  Bhanwar Singh ,  Ramkumar Subramanian

IPC分类号： G01B1106

CPC分类号： H01L21/28194 ,  G01B11/0625 ,  H01L21/67253 ,  H01L29/517 ,  H01L29/518

摘要： A system for regulating gate oxide layer formation is provided. The system includes one or more light sources, each light source directing light to one or more gate oxide layers being deposited and/or formed on a wafer. Light reflected from the gate oxide layers is collected by a measuring system, which processes the collected light. The collected light is indicative of the thickness and/or uniformity of the respective gate oxide layers on the wafer. The measuring system provides thickness and/or uniformity related data to a processor that determines the thickness and/or uniformity of the respective gate oxide layers on the wafer. The system also includes a plurality of gate oxide layer formers where each gate oxide former corresponds to a respective portion of the wafer and provides for gate oxide layer formation thereon. The processor selectively controls the gate oxide layer formers to regulate gate oxide layer formation on the respective gate oxide layer formations on the wafer.

摘要翻译： 提供了一种用于调节栅氧化层形成的系统。 该系统包括一个或多个光源，每个光源将光引导到在晶片上沉积和/或形成的一个或多个栅极氧化物层。 从栅极氧化层反射的光被测量系统收集，该系统处理所收集的光。 所收集的光表示晶片上各个栅极氧化物层的厚度和/或均匀性。 测量系统向处理器提供厚度和/或均匀性相关数据，其确定晶片上各个栅极氧化物层的厚度和/或均匀性。 该系统还包括多个栅极氧化物层形成器，其中每个栅极氧化物形成体对应于晶片的相应部分并且在其上形成栅极氧化物层。 处理器选择性地控制栅极氧化物层形成器以调节在晶片上的各个栅极氧化物层形成上的栅极氧化物层形成。

公开(公告)号：US06685467B1

公开(公告)日：2004-02-03

申请号：US09709827

申请日：2000-11-10

申请人： Ramkumar Subramanian

发明人： Ramkumar Subramanian

IPC分类号： F27D500

CPC分类号： H01L21/67248 ,  F27B17/0025 ,  H01L21/67109

摘要： The invention provides systems and methods for controlling resist baking processes, such as PEB of chemically amplified photoresists. A system of the invention provides a baking plate through which hot fluids and cold fluids may be alternately circulated. The system takes measurements relating to temperature of the baking plate, temperature of the resist, and/or extent of the baking process. Using this data, the system controls the baking temperature and/or the overall extent of the baking process through control over the flow of hot and cold fluids. By alternating between hot and cold fluid circulation, systems of the invention provide rapidly responsive temperature control and/or abrupt termination of baking. Control over the baking process is further increased by implementing flow and process control separately over each of a plurality of different portions of a baking plate.

摘要翻译： 本发明提供了用于控制抗蚀剂烘烤过程的系统和方法，例如化学放大光致抗蚀剂的PEB。 本发明的系统提供一种烘烤板，热流体和冷流体可以通过该烘烤板交替循环。 该系统测量与烘烤板的温度，抗蚀剂的温度和/或烘烤过程的程度有关的测量。 使用这些数据，该系统通过控制热和冷流体的流动来控制烘烤温度和/或烘烤过程的总体程度。 通过在热和冷流体循环之间交替，本发明的系统提供快速响应的温度控制和/或突然终止烘烤。 通过在烘烤板的多个不同部分中的每一个上分别实施流程和过程控制来进一步提高烘烤过程的控制。

公开(公告)号：US06589804B1

公开(公告)日：2003-07-08

申请号：US09904089

申请日：2001-07-12

申请人： Arvind Halliyal ,  Bhanwar Singh ,  Ramkumar Subramanian

发明人： Arvind Halliyal ,  Bhanwar Singh ,  Ramkumar Subramanian

IPC分类号： H01L2100

CPC分类号： G01B11/0625

摘要： A system for regulating ON and/or ONO dielectric formation is provided. The system includes one or more light sources, each light source directing light to one or more oxide and/or nitride layers being deposited and/or formed on a wafer. Light reflected from the oxide and/or nitride layers is collected by a measuring system, which processes the collected light. The collected light is indicative of the thickness and/or uniformity of the respective oxide and/or nitride layers on the wafer. The measuring system provides thickness and/or uniformity related data to a processor that determines the thickness and/or uniformity of the respective oxide and/or nitride layers on the wafer. The system also includes a plurality of oxide/nitride formers; each oxide/nitride former corresponding to a respective portion of the wafer and providing for ON and/or ONO formation thereon. The processor selectively controls the oxide/nitride formers to regulate oxide and/or nitride layer formation on the respective ON and/or ONO formations on the wafer.

摘要翻译： 提供了一种用于调节ON和/或ONO电介质形成的系统。 该系统包括一个或多个光源，每个光源将光引导到在晶片上沉积和/或形成的一个或多个氧化物和/或氮化物层。 从氧化物和/或氮化物层反射的光被测量系统收集，该系统处理收集的光。 所收集的光指示晶片上各个氧化物和/或氮化物层的厚度和/或均匀性。 测量系统向处理器提供厚度和/或均匀性相关数据，其确定晶片上相应氧化物和/或氮化物层的厚度和/或均匀性。 该系统还包括多个氧化物/氮化物成形器; 每个氧化物/氮化物成形器对应于晶片的相应部分并且在其上提供ON和/或ONO形成。 处理器选择性地控制氧化物/氮化物成形器以调节晶片上相应的ON和/或ONO形成上的氧化物和/或氮化物层的形成。

公开(公告)号：US06562248B1

公开(公告)日：2003-05-13

申请号：US09817518

申请日：2001-03-26

申请人： Ramkumar Subramanian ,  Bhanwar Singh ,  Michael K. Templeton

发明人： Ramkumar Subramanian ,  Bhanwar Singh ,  Michael K. Templeton

IPC分类号： G01N2100

CPC分类号： G03F1/84 ,  G03F1/26

摘要： A system for monitoring and controlling aperture etching in a complimentary phase shift mask is provided. The system includes one or more light sources, each light source directing light to one or more apertures etched on a mask. Light reflected from the apertures is collected by a measuring system, which processes the collected light. Light passing through the apertures may similarly be collected by the measuring system, which processes the collected light. The collected light is indicative of the depth and/or width of the openings on the mask. The measuring system provides depth and/or width related data to a processor that determines the acceptability of the aperture depth and/or width. The system also includes a plurality of etching devices associated with etching apertures in the mask. The processor selectively controls the etching devices so as to regulate aperture etching.

摘要翻译： 提供了一种用于在补偿相移掩模中监测和控制孔蚀刻的系统。 该系统包括一个或多个光源，每个光源将光引导到在掩模上蚀刻的一个或多个孔。 从孔径反射的光由测量系统收集，该系统处理所收集的光。 通过孔的光可以类似地由处理收集的光的测量系统收集。 收集的光指示掩模上的开口的深度和/或宽度。 测量系统向确定孔径深度和/或宽度的可接受性的处理器提供深度和/或宽度相关数据。 该系统还包括与掩模中的孔蚀刻相关联的多个蚀刻装置。 处理器选择性地控制蚀刻装置以调节孔径蚀刻。

公开(公告)号：US06562185B2

公开(公告)日：2003-05-13

申请号：US09955552

申请日：2001-09-18

申请人： Steven C. Avanzino ,  Bhanwar Singh ,  Bharath Rangarajan ,  Ramkumar Subramanian

发明人： Steven C. Avanzino ,  Bhanwar Singh ,  Bharath Rangarajan ,  Ramkumar Subramanian

IPC分类号： B24B3700

CPC分类号： B24B37/015

摘要： A system for characterizing a chemical mechanical polishing process is provided. The system includes a wafer that has a metal, polysilicon, and/or dielectric layer and/or substrate and a temperature sensor located in and/or on the metal, polysilicon and/or dielectric layer and/or substrate. The system also includes a temperature monitoring system that can read the wafer temperature from the temperature sensors and that can analyze the wafer temperature to characterize the chemical mechanical polishing process. Such characterization includes producing information concerning relationships between wafer temperature and polishing rate, polishing uniformity and introduction of defects during polishing. Such relationships are correlated with wafer temperature as related to parameters like polishing time, pressure, speed, slurry properties and wafer/metal layer properties. Such characterization can be employed, for example, to better understand a CMP process, to facilitate initializing subsequent chemical mechanical polishing processes and/or apparatus and/or to control such chemical mechanical polishing processes and/or apparatus by monitoring and/or controlling wafer temperature.

摘要翻译： 提供了表征化学机械抛光工艺的系统。 该系统包括具有位于金属，多晶硅和/或电介质层和/或衬底中和/或上的金属，多晶硅和/或电介质层和/或衬底和温度传感器的晶片。 该系统还包括一个温度监控系统，可以从温度传感器读取晶圆温度，并且可以分析晶圆温度以表征化学机械抛光过程。 这种表征包括产生关于晶片温度和抛光速率之间的关系的信息，抛光均匀性和在抛光期间引入缺陷。 这些关系与晶片温度相关，如与抛光时间，压力，速度，浆料性质和晶片/金属层性质等参数相关。 可以采用这种表征，例如，更好地理解CMP工艺，以便于初始化随后的化学机械抛光工艺和/或设备和/或通过监测和/或控制晶片温度来控制这种化学机械抛光工艺和/或设备 。

公开(公告)号：US06509229B1

公开(公告)日：2003-01-21

申请号：US09850484

申请日：2001-05-07

申请人： Fei Wang ,  Ramkumar Subramanian ,  Yu Sun

发明人： Fei Wang ,  Ramkumar Subramanian ,  Yu Sun

IPC分类号： H01L21336

CPC分类号： H01L21/76897 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L2924/3011

摘要： A method for shrinking a semiconductor device is disclosed. An etch stop layer is eliminated and is replaced with a consumable second sidewall spacers so that stacked gate structures of the device can be positioned closer together, thus permitting shrinking of the device. In a preferred embodiment, the present invention provides a method for forming self-aligned contacts by forming multi-layer structures on a region on a semiconductor substrate, forming first sidewall spacers around the multi-layer structures, forming second sidewall spacers around the first sidewall spacers, forming a dielectric layer directly over the substrate and in contact with second sidewall spacers, forming an opening in the dielectric layer to expose a portion of the region on the semiconductor substrate adjacent the second sidewall spacers, and filling the opening with a conductive material to form a contact.

摘要翻译： 公开了一种用于收缩半导体器件的方法。 消除了蚀刻停止层，并且被可消耗的第二侧壁间隔物代替，使得该器件的堆叠栅极结构可以更靠近地放置在一起，从而允许器件收缩。 在优选实施例中，本发明提供了一种通过在半导体衬底上的区域上形成多层结构来形成自对准接触的方法，在多层结构周围形成第一侧墙，围绕第一侧壁形成第二侧壁 间隔物，直接在衬底上形成电介质层并与第二侧壁间隔物接触，在电介质层中形成开口以暴露与第二侧壁间隔物相邻的半导体衬底上的区域的一部分，并用导电材料填充该开口 形成联系。

公开(公告)号：US06507474B1

公开(公告)日：2003-01-14

申请号：US09597126

申请日：2000-06-19

申请人： Bhanwar Singh ,  Ramkumar Subramanian ,  Khoi A. Phan ,  Bryan K. Choo ,  Bharath Rangarajan

发明人： Bhanwar Singh ,  Ramkumar Subramanian ,  Khoi A. Phan ,  Bryan K. Choo ,  Bharath Rangarajan

IPC分类号： H01T2300

CPC分类号： G03F7/70616 ,  G03F7/70941

摘要： One aspect of the present invention elates to a method of reducing electrostatic charges on a patterned photoresist to improve evaluation of the developed photoresist, involving the steps of evaluating the patterned photoresist to determine if electrostatic charges exist thereon; positioning an ionizer near the patterned photoresist, the ionizer generating ions thereby reducing the electrostatic charges on the patterned photoresist; and evaluating the patterned photoresist with an electron beam. Another aspect of the present invention relates to a system for reducing electrostatic charges on a patterned photoresist, containing a charge sensor for determining if electrostatic charges exist on the patterned photoresist and measuring the electrostatic charges; an ionizer positioned near the patterned photoresist having electrostatic charges thereon for reducing the electrostatic charges on the patterned photoresist; a controller for setting at least one of time of ion generation and amount of ion generation by the ionizer, the controller coupled to the charge sensor and the ionizer; and a scanning electron microscope or an atomic force microscope for evaluating the patterned photoresist having reduced electrostatic charges thereon with an electron beam.

摘要翻译： 本发明的一个方面是提供减少图案化光致抗蚀剂上的静电电荷以改进对显影光致抗蚀剂的评估的方法，包括评估图案化光致抗蚀剂以确定静电电荷是否存在于其中的步骤; 在图案化的光致抗蚀剂附近定位电离器，离子发生器产生离子，从而减少图案化光致抗蚀剂上的静电电荷; 并用电子束评估图案化的光致抗蚀剂。 本发明的另一方面涉及一种用于减少图案化光致抗蚀剂上的静电电荷的系统，其包含用于确定图案化光致抗蚀剂上是否存在静电电荷并测量静电电荷的电荷传感器; 位于图案化的光致抗蚀剂附近的电离器，其上具有静电电荷，用于减少图案化光致抗蚀剂上的静电电荷; 用于设置离子发生时间和离子发生量中的至少一个的控制器，耦合到电荷传感器和离子发生器的控制器; 以及扫描电子显微镜或原子力显微镜，用于用电子束评估其上具有降低的静电电荷的图案化光致抗蚀剂。

公开(公告)号：US06492075B1

公开(公告)日：2002-12-10

申请号：US09881993

申请日：2001-06-15

申请人： Michael K. Templeton ,  Ramkumar Subramanian ,  Bharath Rangarajan

发明人： Michael K. Templeton ,  Ramkumar Subramanian ,  Bharath Rangarajan

IPC分类号： G03H900

CPC分类号： G03F7/40 ,  G03F7/405

摘要： In one embodiment, the present invention relates to a method of treating a patterned resist involving the steps of providing the patterned resist having structural features of a first size, the patterned resist containing a polymer having a labile group; contacting a coating containing at least one cleaving compound with the patterned resist to form a thin deprotected resist layer at an interface between the patterned resist and the coating; and removing the coating and the thin deprotected resist layer leaving the patterned resist having structural features of a second size, wherein the second size is smaller than the first size.

摘要翻译： 在一个实施方案中，本发明涉及一种处理图案化抗蚀剂的方法，包括以下步骤：提供具有第一尺寸结构特征的图案化抗蚀剂，所述图案化抗蚀剂含有具有不稳定基团的聚合物; 使含有至少一种裂解化合物的涂层与图案化的抗蚀剂接触以在图案化的抗蚀剂和涂层之间的界面处形成薄的去保护的抗蚀剂层; 以及去除涂层和薄的去保护的抗蚀剂层，留下具有第二尺寸的结构特征的图案化抗蚀剂，其中第二尺寸小于第一尺寸。

公开(公告)号：US06482699B1

公开(公告)日：2002-11-19

申请号：US09685972

申请日：2000-10-10

申请人： YongZhong Hu ,  Fei Wang ,  Wenge Yang ,  Yu Sun ,  Ramkumar Subramanian

发明人： YongZhong Hu ,  Fei Wang ,  Wenge Yang ,  Yu Sun ,  Ramkumar Subramanian

IPC分类号： H01L21336

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L2924/3011

摘要： A method of manufacturing a semiconductor device is provided in which multi-layer structures are formed on a semiconductor substrate to form core and peripheral regions. Sidewall spacers are formed around the multi-layer structures and source and drain regions are implanted adjacent the sidewall spacers and a stop layer is deposited over the semiconductor substrate after which a dielectric layer is deposited over the stop layer. A first and second photoresist contact masks are deposited, processed, and used to respectively etch core and peripheral contact openings. The first and photoresist contact masks are respectively removed after each etching step. A conductive material is deposited over the dielectric layer and in the core and peripheral contact openings and is chemical mechanical planarized to remove the conductive material over the dielectric layer so the conductive material is left isolated in the core and peripheral contact openings with core contacts to the source/drain regions and peripheral contacts to the local interconnect gate contacts of the multi-layer structures and the source/drain regions.

摘要翻译： 提供一种制造半导体器件的方法，其中在半导体衬底上形成多层结构以形成芯和周边区域。 在多层结构周围形成侧壁间隔物，并且将源极和漏极区域相邻于侧壁间隔物注入，并且在半导体衬底上沉积停止层，之后在停止层上沉积电介质层。 第一和第二光致抗蚀剂接触掩模被沉积，处理并用于分别蚀刻芯部和外围接触开口。 在每个蚀刻步骤之后分别去除第一和光致抗蚀剂接触掩模。 导电材料沉积在电介质层上以及芯和外围接触开口中，并进行化学机械平面化以去除电介质层上的导电材料，因此导电材料在核心和外围接触开口中被隔离，其核心接触到 源极/漏极区域和周边接触到多层结构和源极/漏极区域的局部互连栅极触点。

公开(公告)号：US06482558B1

公开(公告)日：2002-11-19

申请号：US09782382

申请日：2001-02-12

申请人： Bhanwar Singh ,  Ramkumar Subramanian ,  Bharath Rangarajan

发明人： Bhanwar Singh ,  Ramkumar Subramanian ,  Bharath Rangarajan

IPC分类号： G03F900

CPC分类号： G03F7/093 ,  G03F1/40 ,  G03F1/50 ,  Y10S430/143

摘要： One aspect of the present invention relates to a system for dissipating electrostatic charge on a mask plate structure containing the mask plate structure containing a substrate, a chromium layer over the substrate, and a conductive polymer over the chromium layer; a conductive structure coupled to the mask plate structure which allows accumulated electrostatic charge to flow from the mask plate structure; a conductive path between the conductive structure and a ground, wherein the conductive path inacludes a switch controlled by a controller; and a detector coupled to the controller for signaling the controller when the accumulation of electrostatic charge is detected. Another aspect of the present invention relates to a method for dissipating charge accumulation during patterning of mask plates using a conductive polymer layer involving the steps of providing a mask substrate having a chromium layer; depositing a conductive polymer layer over the chromium layer; connecting a conductive structure to the mask substrate; irradiating portions of the mask substrate with an electron beam; detecting whether electrostatic charge exists on the mask substrate; and if electrostatic charge is detected, closing a circuit whereby the conductive structure is grounded to permit a flow of electrostatic charge from the mask substrate to the ground.

摘要翻译： 本发明的一个方面涉及一种用于在掩模板结构上耗散静电电荷的系统，该系统包含含有衬底的掩模板结构，在衬底上的铬层和在铬层上的导电聚合物; 耦合到掩模板结构的导电结构，其允许积聚的静电电荷从掩模板结构流动; 导电结构和地之间的导电路径，其中导电路径不允许由控制器控制的开关; 以及耦合到控制器的检测器，用于在检测到静电电荷的累积时用于发信号通知控制器。 本发明的另一方面涉及一种使用导电聚合物层在掩模板图案化期间耗散电荷累积的方法，包括以下步骤：提供具有铬层的掩模基板; 在所述铬层上沉积导电聚合物层; 将导电结构连接到所述掩模基板; 用电子束照射掩模基板的部分; 检测在掩模基板上是否存在静电电荷; 并且如果检测到静电电荷，则关闭电路，由此导电结构接地以允许静电电荷从掩模基板流到地面。