公开(公告)号：US08149038B1

公开(公告)日：2012-04-03

申请号：US12729114

申请日：2010-03-22

申请人： Chiakang Sung ,  John Henry Bui ,  Khai Nguyen ,  Bonnie I. Wang ,  Xiaobao Wang

发明人： Chiakang Sung ,  John Henry Bui ,  Khai Nguyen ,  Bonnie I. Wang ,  Xiaobao Wang

IPC分类号： H03H11/16

CPC分类号： H03L7/0814 ,  H03K2005/00293

摘要： A dynamic phase alignment circuit includes a phase generator circuit having delay-locked loop circuits that generate periodic output signals. Each of the delay-locked loop circuits generates one of the periodic output signals in response to at least two periodic input signals. A multiplexer circuit selects a selected periodic signal from among the periodic input signals and the periodic output signals based on select signals. A phase detection circuit compares a phase of the selected periodic signal to a data signal to generate a phase detection signal. A control logic circuit generates the select signals. The control logic circuit adjusts the select signals based on changes in the phase detection signal to cause the multiplexer circuit to adjust the phase of the selected periodic signal.

摘要翻译： 动态相位对准电路包括具有产生周期性输出信号的延迟锁定环路电路的相位发生器电路。 每个延迟锁定环路电路响应于至少两个周期性输入信号产生周期性输出信号之一。 多路复用器电路基于选择信号从周期性输入信号和周期性输出信号中选择选定的周期信号。 相位检测电路将选择的周期信号的相位与数据信号进行比较，以产生相位检测信号。 控制逻辑电路产生选择信号。 控制逻辑电路基于相位检测信号的变化来调整选择信号，以使多路复用器电路调整所选周期信号的相位。

公开(公告)号：US08022723B1

公开(公告)日：2011-09-20

申请号：US11458675

申请日：2006-07-19

申请人： Xiaobao Wang ,  Bonnie I. Wang ,  Chiakang Sung ,  Khai Q. Nguyen

发明人： Xiaobao Wang ,  Bonnie I. Wang ,  Chiakang Sung ,  Khai Q. Nguyen

IPC分类号： H03K17/16

CPC分类号： H04L25/0298 ,  H04L25/0278

摘要： Circuits, methods, and apparatus for dynamic control of source and termination impedances. One output stage provides a series termination when transmitting and a parallel termination when receiving data. A pull-up device has a nominal impedance of 50 ohms when the output stage pulls a pin from a low voltage to a high voltage, while a pull-down device has a nominal impedance of 50 ohms when the pin is pulled from a high voltage to a low voltage. Both the pull-up and pull-down devices are turned on when receiving data. Due to their non-linear current-voltage characteristics, the pull-up device appears as 50 ohms when the pin voltage is higher than one half the supply voltage, while the pull-down device appears as 50 ohms when the pin voltage is lower than one half the supply voltage. The pull-up and pull-down devices can be calibrated to provide a nominal 50 ohm impedance.

摘要翻译： 用于动态控制源和端接阻抗的电路，方法和装置。 一个输出级在发送时提供串联终止，并在接收数据时提供并行终止。 当输出级将引脚从低电压拉到高电平时，上拉器件的标称阻抗为50欧姆，而当引脚从高电压拉出时，下拉器件的标称阻抗为50欧姆 到低电压。 上拉和下拉设备在接收数据时都打开。 由于其非线性电流 - 电压特性，当引脚电压高于电源电压的一半时，上拉器件显示为50欧姆，而当引脚电压低于50欧姆时，下拉器件显示为50欧姆 电源电压的一半。 可以校准上拉和下拉器件以提供标称的50欧姆阻抗。

公开(公告)号：US08610462B1

公开(公告)日：2013-12-17

申请号：US13332730

申请日：2011-12-21

申请人： Xiaobao Wang ,  Chiakang Sung ,  Khai Nguyen ,  Bonnie I. Wang

发明人： Xiaobao Wang ,  Chiakang Sung ,  Khai Nguyen ,  Bonnie I. Wang

IPC分类号： H03K19/094 ,  H03K19/0175 ,  H03K3/00 ,  H03B1/00

CPC分类号： H03K3/356113

摘要： Circuits and techniques for operating an integrated circuit (IC) with a level shifter circuit are disclosed. A level shifter circuit with input and output terminals is operable to shift an input signal that ranges from a ground voltage to a first positive voltage to an output signal that ranges from the ground voltage to a second positive voltage. The level shifter circuit further includes a first kicker transistor having a first source-drain terminal operable to receive a buffered version of the input signal and having a second source-drain terminal coupled to the output terminal. The first kicker transistor may receive gate signals that turn on the first kicker transistor when the input signal is at the ground voltage and may pull the output terminal to the first positive voltage as the input signal transitions from the ground voltage to the first positive voltage.

摘要翻译： 公开了用于利用电平移位器电路来操作集成电路（IC）的电路和技术。 具有输入和输出端子的电平移位器电路可操作以将从地电压到第一正电压的输入信号移动到范围从接地电压到第二正电压的输出信号。 电平移位器电路还包括具有第一源极 - 漏极端子的第一汲取晶体管，第一源极 - 漏极端子可操作以接收缓冲版本的输入信号并具有耦合到输出端子的第二源极 - 漏极端子。 当输入信号处于接地电压时，第一icker晶体晶体管可以接收导通第一猝发晶体管的栅极信号，并且当输入信号从接地电压转变到第一正电压时，可以将输出端拉至第一正电压。

公开(公告)号：US07973553B1

公开(公告)日：2011-07-05

申请号：US12721759

申请日：2010-03-11

申请人： Xiaobao Wang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen ,  John Henry Bui

发明人： Xiaobao Wang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen ,  John Henry Bui

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H04L25/0278

摘要： A circuit includes first transistors and a comparator. The comparator compares a reference signal and a signal that is based on conductive states of the first transistors. A control circuit generates first control signals based on an output signal of the comparator. The conductive states of the first transistors are determined based on the first control signals. An arithmetic circuit performs an arithmetic function based on the first control signals and second control signals to generate calibration signals. Second transistors provide a termination impedance at an external terminal of the circuit that is based on the calibration signals.

摘要翻译： 电路包括第一晶体管和比较器。 比较器比较参考信号和基于第一晶体管的导电状态的信号。 控制电路根据比较器的输出信号产生第一控制信号。 基于第一控制信号来确定第一晶体管的导通状态。 算术电路基于第一控制信号和第二控制信号执行运算功能，以生成校准信号。 第二晶体管在基于校准信号的电路的外部端子处提供终端阻抗。

公开(公告)号：US07551014B1

公开(公告)日：2009-06-23

申请号：US11670109

申请日：2007-02-01

申请人： Bonnie I. Wang ,  Chiakang Sung ,  Khai Nguyen ,  Xiaobao Wang

发明人： Bonnie I. Wang ,  Chiakang Sung ,  Khai Nguyen ,  Xiaobao Wang

IPC分类号： G06F7/44

CPC分类号： H04L25/0272

摘要： Circuits and methods provide single-ended and differential signals. Single-ended drivers are used to, e.g., reduce pin capacitance. The output cell uses an inversion circuit, such as a phase splitter, to derive the differential signals from the same output signal and provide low skew between the differential signals at the output pins. Selection circuits are used to select between single-ended and differential output.

摘要翻译： 电路和方法提供单端和差分信号。 单端驱动器用于例如降低引脚电容。 输出单元使用诸如分相器的反相电路从相同的输出信号导出差分信号，并在输出引脚之间的差分信号之间提供低偏差。 选择电路用于在单端和差分输出之间进行选择。

公开(公告)号：US07026847B2

公开(公告)日：2006-04-11

申请号：US10749883

申请日：2003-12-31

申请人： Bonnie I. Wang ,  Chiakang Sung ,  Khai Q. Nguyen ,  Xiaobao Wang

发明人： Bonnie I. Wang ,  Chiakang Sung ,  Khai Q. Nguyen ,  Xiaobao Wang

IPC分类号： H03K3/00

CPC分类号： H03K19/01707 ,  H03K19/0016 ,  H03K19/01721 ,  H03K19/018507

摘要： An AC current booster for high speed, high frequency applications having a single-ended output embodiment and a differential output embodiment. The embodiments of the present invention allow bifurcated control of the AC switching rate and the DC state of a given output signal, in order to achieve faster rising and falling edge rates without an undesirable increase in output voltage swing.

摘要翻译： 用于具有单端输出实施例和差分输出实施例的高速，高频应用的AC电流增压器。 本发明的实施例允许对给定输出信号的AC开关速率和DC状态的分叉控制，以便实现更快的上升和下降沿速率，而不会不期望地增加输出电压摆幅。

公开(公告)号：US5768372A

公开(公告)日：1998-06-16

申请号：US617664

申请日：1996-03-13

申请人： Chiakang Sung ,  Bonnie I. Wang

发明人： Chiakang Sung ,  Bonnie I. Wang

IPC分类号： G06F1/00 ,  G06F21/00 ,  H03K19/177 ,  H04L9/00 ,  H03K19/007

CPC分类号： H03K19/17768 ,  G06F21/6209 ,  G06F21/79 ,  G06F2221/2107 ,  G06F2221/2113

摘要： An SRAM-based programmable logic device having decompression and decryption circuits between its EPROM nonvolatile programming data storage and its SRAM programming registers is secured against copying of the programming data because a would-be copyist would need to know the compression and encryption used. In a system and method for programming the device, a user station preferably contains a plurality of possible encryptions and a plurality of possible compression schemes. An encryption and compression scheme are selected, preferably at random, by the user or by the programming software in the user station. Data indicating which encryption and compression scheme were chosen are included in the programming data to allow decompression and decryption.

摘要翻译： 在其EPROM非易失性编程数据存储器及其SRAM编程寄存器之间具有解压缩和解密电路的基于SRAM的可编程逻辑器件被保护以防止编程数据的复制，因为将要存档的抄写员将需要知道使用的压缩和加密。 在用于对该设备进行编程的系统和方法中，用户站优选地包含多个可能的加密和多个可能的压缩方案。 优选地由用户或用户站中的编程软件随机地选择加密和压缩方案。 指示哪个加密和压缩方案被选择的数据被包括在编程数据中以允许解压缩和解密。

公开(公告)号：US07304501B2

公开(公告)日：2007-12-04

申请号：US11251099

申请日：2005-10-14

申请人： Xiaobao Wang ,  Khai Q. Nguyen ,  Chiakang Sung ,  Bonnie I. Wang

发明人： Xiaobao Wang ,  Khai Q. Nguyen ,  Chiakang Sung ,  Bonnie I. Wang

IPC分类号： H03K19/00 ,  H03K19/08

CPC分类号： H03K19/00315

摘要： The hot socket detect circuit of the present invention includes a well bias circuit and three hot socket detect blocks. If the output of any of the three hot socket detect blocks is a digital high signal then the output of the hot socket detect circuit is a digital high signal. The digital high signal indicates that a hot socket condition exists.

公开(公告)号：US5915017A

公开(公告)日：1999-06-22

申请号：US7130

申请日：1998-01-14

申请人： Chiakang Sung ,  Bonnie I. Wang

发明人： Chiakang Sung ,  Bonnie I. Wang

IPC分类号： G06F1/00 ,  G06F21/00 ,  H03K19/177 ,  H04L9/00 ,  H03K19/007

CPC分类号： H03K19/17768 ,  G06F21/6209 ,  G06F21/79 ,  G06F2221/2107 ,  G06F2221/2113

摘要： An SRAM-based programmable logic device having decompression and decryption circuits between its EPROM nonvolatile programming data storage and its SRAM programming registers is secured against copying of the programming data because a would-be copyist would need to know the compression and encryption used. In a system and method for programming the device, a user station preferably contains a plurality of possible encryptions and a plurality of possible compression schemes. An encryption and compression scheme are selected, preferably at random, by the user or by the programming software in the user station. Data indicating which encryption and compression scheme were chosen are included in the programming data to allow decompression and decryption.

摘要翻译： 在其EPROM非易失性编程数据存储器及其SRAM编程寄存器之间具有解压缩和解密电路的基于SRAM的可编程逻辑器件被保护以防止编程数据的复制，因为将要存档的抄写员将需要知道使用的压缩和加密。 在用于对该设备进行编程的系统和方法中，用户站优选地包含多个可能的加密和多个可能的压缩方案。 优选地由用户或用户站中的编程软件随机地选择加密和压缩方案。 指示哪个加密和压缩方案被选择的数据被包括在编程数据中以允许解压缩和解密。

公开(公告)号：US5592102A

公开(公告)日：1997-01-07

申请号：US545437

申请日：1995-10-19

申请人： Christopher F. Lane ,  Srinivas T. Reddy ,  Bonnie I. Wang

发明人： Christopher F. Lane ,  Srinivas T. Reddy ,  Bonnie I. Wang

IPC分类号： G06F11/20 ,  G06F15/78 ,  H03K19/177 ,  H01L25/00

CPC分类号： H03K19/1776 ,  G06F15/7867 ,  H03K19/17736 ,  H03K19/17764

摘要： A programmable logic array integrated circuit has several regular columns of programmable logic circuitry and a spare column which includes a subset of the programmable logic circuitry that is included in a regular column. In the event of a defect in the circuitry in a regular column that is duplicated in the spare column, the regular column logic functions that are thus duplicated are shifted from column to column so that the spare column circuitry is put to use and the defective regular column circuitry is not used. Regular column functions that are not duplicated in the spare column are not shifted. Data for programming the columns is selectively routed to the columns with or without column shifting, depending on whether that data is for functions that are or are not duplicated in the spare column.

摘要翻译： 可编程逻辑阵列集成电路具有几个可编程逻辑电路的常规列和备用列，该备用列包括包含在常规列中的可编程逻辑电路的子集。 在备用列中复制的常规列中的电路中存在缺陷的情况下，由此复制的常规列逻辑功能从列移动到列，使得备用列电路被使用，并且缺陷规则 不使用列电路。 在备用列中未重复的常规列函数不会移动。 用于编程列的数据有选择地路由到具有或不具有列移位的列，这取决于该数据是用于在备用列中是否被复制的功能。