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    Systems and methods for on-chip impedance termination
    1.
    发明授权
    Systems and methods for on-chip impedance termination 有权
    用于片上阻抗终止的系统和方法

    公开(公告)号：US06603329B1

    公开(公告)日：2003-08-05

    申请号：US10044459

    申请日：2002-01-11

    申请人： Xiaobao Wang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen

    发明人： Xiaobao Wang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen

    IPC分类号： H03K1716

    CPC分类号： H04L25/0278 ,  H04L25/0298

    摘要： Techniques for on-chip impedance termination are provided that substantially reduce the number of external resistors that are need to provide impedance termination at a plurality of pairs of differential input/output (I/O) pins. On-chip impedance termination circuits of the present invention may include an amplifier, a feedback loop, and an impedance termination circuit. A reference voltage is provided to a first input terminal of the amplifier. A feedback loop is coupled between an output terminal of the amplifier and a second input terminal of the amplifier. The amplifier drives its output voltage so that the voltage at the second input terminal matches the voltage at the first input terminal. The output voltage of the amplifier determines the resistance of the impedance termination circuit. The impedance termination circuit is coupled between differential I/O pins.

    摘要翻译： 提供用于片上阻抗终止的技术，其大大减少了需要在多对差分输入/输出（I / O）引脚上提供阻抗终端的外部电阻器的数量。 本发明的片上阻抗终端电路可以包括放大器，反馈回路和阻抗终端电路。 将参考电压提供给放大器的第一输入端。 反馈回路耦合在放大器的输出端和放大器的第二输入端之间。 放大器驱动其输出电压，使得第二输入端子处的电压与第一输入端子处的电压匹配。 放大器的输出电压决定了阻抗终端电路的电阻。 阻抗端接电路耦合在差分I / O引脚之间。

    High-speed programmable interconnect
    3.
    发明授权
    High-speed programmable interconnect 有权
    高速可编程互连

    公开(公告)号：US06384629B2

    公开(公告)日：2002-05-07

    申请号：US09738403

    申请日：2000-12-15

    申请人： Joseph Huang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen ,  Xiaobao Wang ,  Richard G. Cliff

    发明人： Joseph Huang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen ,  Xiaobao Wang ,  Richard G. Cliff

    IPC分类号： H01L2500

    CPC分类号： H03K19/17736 ,  G01R31/318555 ,  G06F11/2273 ,  H03K19/17792

    摘要： An improved interconnection between horizontal conductors and the input to logic elements. A signal regeneration circuit is provided in the path between the horizontal conductor and the logic element, thereby isolating and boosting the signal. This allows for faster switching operation. A path is provided allowing the selective routing of signals from the horizontal conductors to the vertical conductors, without passing through a logic element. Also, a path is provided to allow a horizontal conductors to be routed to any of a plurality of vertical conductors.

    摘要翻译： 水平导体与逻辑元件输入之间的互连改善。 在水平导体和逻辑元件之间的路径中提供信号再生电路，从而隔离和升高信号。 这允许更快的切换操作。 提供路径，允许从水平导体到垂直导体的信号的选择性路由，而不通过逻辑元件。 而且，提供了一种路径，以允许水平导体被路由到多个垂直导体中的任何一个。

    Techniques for phase adjustment
    4.
    发明授权
    Techniques for phase adjustment 有权
    相位调整技术

    公开(公告)号：US08384460B1

    公开(公告)日：2013-02-26

    申请号：US13420349

    申请日：2012-03-14

    申请人： Chiakang Sung ,  John Henry Bui ,  Khai Nguyen ,  Bonnie I. Wang ,  Xiaobao Wang

    发明人： Chiakang Sung ,  John Henry Bui ,  Khai Nguyen ,  Bonnie I. Wang ,  Xiaobao Wang

    IPC分类号： H03H11/16

    CPC分类号： H03L7/0814 ,  H03K2005/00293

    摘要： An adjustable delay circuit includes first and second transistors each having a control input coupled to an input node of the adjustable delay circuit and an output coupled to an output node of the adjustable delay circuit. The adjustable delay circuit includes a first pass gate coupled between first and second capacitors and the output node of the adjustable delay circuit. The first and the second capacitors are coupled between a node at a high voltage and a node at a low voltage. The first pass gate is operable to be controlled by a first delay control signal.

    摘要翻译： 可调延迟电路包括第一和第二晶体管，每个晶体管具有耦合到可调延迟电路的输入节点的控制输入和耦合到可调延迟电路的输出节点的输出。 可调延迟电路包括耦合在第一和第二电容器之间的第一通过栅极和可调延迟电路的输出节点。 第一和第二电容器耦合在高电压节点和低电压节点之间。 第一通过门可操作以由第一延迟控制信号控制。

    Techniques for phase adjustment
    5.
    发明授权
    Techniques for phase adjustment 有权
    相位调整技术

    公开(公告)号：US08149038B1

    公开(公告)日：2012-04-03

    申请号：US12729114

    申请日：2010-03-22

    申请人： Chiakang Sung ,  John Henry Bui ,  Khai Nguyen ,  Bonnie I. Wang ,  Xiaobao Wang

    发明人： Chiakang Sung ,  John Henry Bui ,  Khai Nguyen ,  Bonnie I. Wang ,  Xiaobao Wang

    IPC分类号： H03H11/16

    CPC分类号： H03L7/0814 ,  H03K2005/00293

    摘要： A dynamic phase alignment circuit includes a phase generator circuit having delay-locked loop circuits that generate periodic output signals. Each of the delay-locked loop circuits generates one of the periodic output signals in response to at least two periodic input signals. A multiplexer circuit selects a selected periodic signal from among the periodic input signals and the periodic output signals based on select signals. A phase detection circuit compares a phase of the selected periodic signal to a data signal to generate a phase detection signal. A control logic circuit generates the select signals. The control logic circuit adjusts the select signals based on changes in the phase detection signal to cause the multiplexer circuit to adjust the phase of the selected periodic signal.

    摘要翻译： 动态相位对准电路包括具有产生周期性输出信号的延迟锁定环路电路的相位发生器电路。 每个延迟锁定环路电路响应于至少两个周期性输入信号产生周期性输出信号之一。 多路复用器电路基于选择信号从周期性输入信号和周期性输出信号中选择选定的周期信号。 相位检测电路将选择的周期信号的相位与数据信号进行比较，以产生相位检测信号。 控制逻辑电路产生选择信号。 控制逻辑电路基于相位检测信号的变化来调整选择信号，以使多路复用器电路调整所选周期信号的相位。

    Programmable logic device input/output circuit configurable as reference voltage input circuit
    7.
    发明授权
    Programmable logic device input/output circuit configurable as reference voltage input circuit 有权
    可编程逻辑器件输入/输出电路可配置为参考电压输入电路

    公开(公告)号：US06346827B1

    公开(公告)日：2002-02-12

    申请号：US09366937

    申请日：1999-08-04

    申请人： Wayne Yeung ,  Chiakang Sung ,  Myron W. Wong ,  Khai Nguyen ,  Bonnie I. Wang ,  Xiaobao Wang ,  Joseph Huang ,  In Whan Kim

    发明人： Wayne Yeung ,  Chiakang Sung ,  Myron W. Wong ,  Khai Nguyen ,  Bonnie I. Wang ,  Xiaobao Wang ,  Joseph Huang ,  In Whan Kim

    IPC分类号： H01L2500

    CPC分类号： G11C5/147 ,  G11C5/066

    摘要： A programmable input/output circuit for a programmable logic device input/output pin can be configured in a standard I/O mode, or in a reference voltage mode. The circuit includes a tristatable, but otherwise standard I/O buffer as well as a reference voltage clamp circuit. In reference voltage mode, the I/O circuit is tristated, and the reference voltage clamp circuit passes a reference voltage from the I/O pin to a reference voltage bus. In standard I/O mode, the I/O buffer is operational. The reference voltage clamp circuit isolates the I/O pin from the reference voltage bus and may include undervoltage and overvoltage protection to prevent disturbance of the reference voltage bus by an out-of-range I/O signal.

    摘要翻译： 可编程逻辑器件输入/输出引脚的可编程输入/输出电路可以在标准I / O模式或参考电压模式下进行配置。 该电路包括可跟踪的标准I / O缓冲器以及参考电压钳位电路。 在参考电压模式下，I / O电路被三态化，参考电压钳位电路将参考电压从I / O引脚传递到参考电压总线。 在标准I / O模式下，I / O缓冲区可以运行。 参考电压钳位电路将I / O引脚与参考电压总线隔离，并可能包括欠压和过压保护，以防止参考电压总线受到超出范围I / O信号的干扰。

    Programmable output buffer
    8.
    发明授权
    Programmable output buffer 有权
    可编程输出缓冲器

    公开(公告)号：US08531205B1

    公开(公告)日：2013-09-10

    申请号：US13363108

    申请日：2012-01-31

    申请人： Bonnie I. Wang ,  Chiakang Sung ,  Xiaobao Wang ,  Khai Nguyen ,  Joseph Huang

    发明人： Bonnie I. Wang ,  Chiakang Sung ,  Xiaobao Wang ,  Khai Nguyen ,  Joseph Huang

    IPC分类号： H03K17/16

    CPC分类号： H03K19/0005 ,  H03K19/018585 ,  H03K19/17744 ,  H03K19/17788

    摘要： One embodiment relates to a programmable output buffer which includes first and second programmable variable-impedance single-ended driver circuits and first and second termination circuits. The first termination circuit is coupled to a first output pin which is driven by the first programmable variable-impedance single-ended driver circuit, and the second termination circuit is coupled to a second output pin which is driven by the second programmable variable-impedance single-ended driver circuit. The first and second termination circuits are programmable to either provide parallel termination for a differential signal or drive single-ended signals with the parallel termination turned off. Other embodiments and features are also disclosed.

    摘要翻译： 一个实施例涉及可编程输出缓冲器，其包括第一和第二可编程可变阻抗单端驱动器电路以及第一和第二终端电路。 第一终端电路耦合到由第一可编程可变阻抗单端驱动电路驱动的第一输出引脚，第二终端电路耦合到由第二可编程可变阻抗单端驱动的第二输出引脚 驱动电路。 第一和第二终端电路是可编程的，以提供用于差分信号的并行终端或者并联终端关断的驱动单端信号。 还公开了其它实施例和特征。

    On-chip impedance matching circuit
    10.
    发明授权
    On-chip impedance matching circuit 有权
    片内阻抗匹配电路

    公开(公告)号：US06798237B1

    公开(公告)日：2004-09-28

    申请号：US10044365

    申请日：2002-01-11

    申请人： Xiaobao Wang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen

    发明人： Xiaobao Wang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen

    IPC分类号： H03K1716

    CPC分类号： H04L25/0278

    摘要： Integrated circuits with on-chip impedance matching techniques, which greatly reduce the number of off-chip resistors that are coupled to the integrated circuit, are provided. On-chip impedance matching circuits of the present invention are associated with each of a plurality of I/O pins on an integrated circuit. Circuitry of the present invention may include a resistor divider that has a resistor and an on-chip transistor. The resistance of the on-chip transistor and a voltage output signal of the resistor divider vary with process, temperature, and voltage of the integrated circuit. The effective channel W/L ratio of the impedance matching circuit changes in response to the voltage output signal of the resistor divider, so that changes in the impedance of the impedance matching circuit caused by the variations in process, temperature, and voltage are minimized.

    摘要翻译： 提供具有片上阻抗匹配技术的集成电路，其大大减少耦合到集成电路的片外电阻器的数量。 本发明的片上阻抗匹配电路与集成电路上的多个I / O引脚中的每一个相关联。 本发明的电路可以包括具有电阻器和片上晶体管的电阻分压器。 片上晶体管的电阻和电阻分压器的电压输出信号随集成电路的工艺，温度和电压而变化。 阻抗匹配电路的有效通道W / L比随着电阻分压器的电压输出信号而变化，使得由过程，温度和电压变化引起的阻抗匹配电路的阻抗变化最小化。