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    Dynamic termination-impedance control for bidirectional I/O pins
    1.
    发明授权
    Dynamic termination-impedance control for bidirectional I/O pins 有权
    用于双向I / O引脚的动态终端阻抗控制

    公开(公告)号：US08854078B1

    公开(公告)日：2014-10-07

    申请号：US13223989

    申请日：2011-09-01

    申请人： Xiaobao Wang ,  Bonnie I. Wang ,  Chiakang Sung ,  Khai Q. Nguyen

    发明人： Xiaobao Wang ,  Bonnie I. Wang ,  Chiakang Sung ,  Khai Q. Nguyen

    IPC分类号： H03K17/16

    CPC分类号： H04L25/0298 ,  H04L25/0278

    摘要： Circuits, methods, and apparatus for dynamic control of source and termination impedances. One output stage provides a series termination when transmitting and a parallel termination when receiving data. A pull-up device has a nominal impedance of 50 ohms when the output stage pulls a pin from a low voltage to a high voltage, while a pull-down device has a nominal impedance of 50 ohms when the pin is pulled from a high voltage to a low voltage. Both the pull-up and pull-down devices are turned on when receiving data. Due to their non-linear current-voltage characteristics, the pull-up device appears as 50 ohms when the pin voltage is higher than one half the supply voltage, while the pull-down device appears as 50 ohms when the pin voltage is lower than one half the supply voltage. The pull-up and pull-down devices can be calibrated to provide a nominal 50 ohm impedance.

    摘要翻译： 用于动态控制源和端接阻抗的电路，方法和装置。 一个输出级在发送时提供串联终止，并在接收数据时提供并行终止。 当输出级将引脚从低电压拉到高电平时，上拉器件的标称阻抗为50欧姆，而当引脚从高电压拉出时，下拉器件的标称阻抗为50欧姆 到低电压。 上拉和下拉设备在接收数据时都打开。 由于其非线性电流 - 电压特性，当引脚电压高于电源电压的一半时，上拉器件显示为50欧姆，而当引脚电压低于50欧姆时，下拉器件显示为50欧姆 电源电压的一半。 可以校准上拉和下拉器件以提供标称的50欧姆阻抗。

    Dynamic termination-impedance control for bidirectional I/O pins
    2.
    发明授权
    Dynamic termination-impedance control for bidirectional I/O pins 有权
    用于双向I / O引脚的动态终端阻抗控制

    公开(公告)号：US08022723B1

    公开(公告)日：2011-09-20

    申请号：US11458675

    申请日：2006-07-19

    申请人： Xiaobao Wang ,  Bonnie I. Wang ,  Chiakang Sung ,  Khai Q. Nguyen

    发明人： Xiaobao Wang ,  Bonnie I. Wang ,  Chiakang Sung ,  Khai Q. Nguyen

    IPC分类号： H03K17/16

    CPC分类号： H04L25/0298 ,  H04L25/0278

    摘要： Circuits, methods, and apparatus for dynamic control of source and termination impedances. One output stage provides a series termination when transmitting and a parallel termination when receiving data. A pull-up device has a nominal impedance of 50 ohms when the output stage pulls a pin from a low voltage to a high voltage, while a pull-down device has a nominal impedance of 50 ohms when the pin is pulled from a high voltage to a low voltage. Both the pull-up and pull-down devices are turned on when receiving data. Due to their non-linear current-voltage characteristics, the pull-up device appears as 50 ohms when the pin voltage is higher than one half the supply voltage, while the pull-down device appears as 50 ohms when the pin voltage is lower than one half the supply voltage. The pull-up and pull-down devices can be calibrated to provide a nominal 50 ohm impedance.

    摘要翻译： 用于动态控制源和端接阻抗的电路，方法和装置。 一个输出级在发送时提供串联终止，并在接收数据时提供并行终止。 当输出级将引脚从低电压拉到高电平时，上拉器件的标称阻抗为50欧姆，而当引脚从高电压拉出时，下拉器件的标称阻抗为50欧姆 到低电压。 上拉和下拉设备在接收数据时都打开。 由于其非线性电流 - 电压特性，当引脚电压高于电源电压的一半时，上拉器件显示为50欧姆，而当引脚电压低于50欧姆时，下拉器件显示为50欧姆 电源电压的一半。 可以校准上拉和下拉器件以提供标称的50欧姆阻抗。

    Self-compensating delay chain for multiple-date-rate interfaces
    5.
    发明授权
    Self-compensating delay chain for multiple-date-rate interfaces 有权
    多速率接口的自补偿延迟链

    公开(公告)号：US07200769B1

    公开(公告)日：2007-04-03

    申请号：US10037861

    申请日：2002-01-02

    申请人： Yan Chong ,  Chiakang Sung ,  Bonnie I. Wang ,  Joseph Huang ,  Xiaobao Wang ,  Philip Pan ,  Tzung-Chin Chang

    发明人： Yan Chong ,  Chiakang Sung ,  Bonnie I. Wang ,  Joseph Huang ,  Xiaobao Wang ,  Philip Pan ,  Tzung-Chin Chang

    IPC分类号： G06F1/04

    CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222 ,  G11C2207/108 ,  H03L7/0805 ,  H03L7/0814 ,  H03L7/091

    摘要： Methods and apparatus for delaying a clock signal for a multiple-data-rate interface. An apparatus provides an integrated circuit including a frequency divider configured to receive a first clock signal and a first variable-delay block configured to receive an output from the frequency divider. Also included is a phase detector configured to receive the first clock signal and an output from the first variable-delay block, and an up/down counter configured to receive an output from the phase detector. A second variable-delay block is configured to receive a second clock signal and a plurality of flip-flops are configured to receive an output from the second variable-delay block. The first variable-delay block and the second variable-delay block are configured to receive an output from the up/down counter.

    摘要翻译： 用于延迟多数据速率接口的时钟信号的方法和装置。 一种装置提供一种集成电路，其包括配置成接收第一时钟信号的分频器和被配置为接收来自分频器的输出的第一可变延迟块。 还包括相位检测器，被配置为接收第一时钟信号和来自第一可变延迟块的输出，以及配置为接收来自相位检测器的输出的上/下计数器。 第二可变延迟块被配置为接收第二时钟信号，并且多个触发器被配置为从第二可变延迟块接收输出。 第一可变延迟块和第二可变延迟块被配置为从加/减计数器接收输出。

    Systems and methods for on-chip impedance termination
    6.
    发明授权
    Systems and methods for on-chip impedance termination 有权
    用于片上阻抗终止的系统和方法

    公开(公告)号：US06603329B1

    公开(公告)日：2003-08-05

    申请号：US10044459

    申请日：2002-01-11

    申请人： Xiaobao Wang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen

    发明人： Xiaobao Wang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen

    IPC分类号： H03K1716

    CPC分类号： H04L25/0278 ,  H04L25/0298

    摘要： Techniques for on-chip impedance termination are provided that substantially reduce the number of external resistors that are need to provide impedance termination at a plurality of pairs of differential input/output (I/O) pins. On-chip impedance termination circuits of the present invention may include an amplifier, a feedback loop, and an impedance termination circuit. A reference voltage is provided to a first input terminal of the amplifier. A feedback loop is coupled between an output terminal of the amplifier and a second input terminal of the amplifier. The amplifier drives its output voltage so that the voltage at the second input terminal matches the voltage at the first input terminal. The output voltage of the amplifier determines the resistance of the impedance termination circuit. The impedance termination circuit is coupled between differential I/O pins.

    摘要翻译： 提供用于片上阻抗终止的技术，其大大减少了需要在多对差分输入/输出（I / O）引脚上提供阻抗终端的外部电阻器的数量。 本发明的片上阻抗终端电路可以包括放大器，反馈回路和阻抗终端电路。 将参考电压提供给放大器的第一输入端。 反馈回路耦合在放大器的输出端和放大器的第二输入端之间。 放大器驱动其输出电压，使得第二输入端子处的电压与第一输入端子处的电压匹配。 放大器的输出电压决定了阻抗终端电路的电阻。 阻抗端接电路耦合在差分I / O引脚之间。

    High-speed programmable interconnect
    7.
    发明授权
    High-speed programmable interconnect 有权
    高速可编程互连

    公开(公告)号：US06384629B2

    公开(公告)日：2002-05-07

    申请号：US09738403

    申请日：2000-12-15

    申请人： Joseph Huang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen ,  Xiaobao Wang ,  Richard G. Cliff

    发明人： Joseph Huang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen ,  Xiaobao Wang ,  Richard G. Cliff

    IPC分类号： H01L2500

    CPC分类号： H03K19/17736 ,  G01R31/318555 ,  G06F11/2273 ,  H03K19/17792

    摘要： An improved interconnection between horizontal conductors and the input to logic elements. A signal regeneration circuit is provided in the path between the horizontal conductor and the logic element, thereby isolating and boosting the signal. This allows for faster switching operation. A path is provided allowing the selective routing of signals from the horizontal conductors to the vertical conductors, without passing through a logic element. Also, a path is provided to allow a horizontal conductors to be routed to any of a plurality of vertical conductors.

    摘要翻译： 水平导体与逻辑元件输入之间的互连改善。 在水平导体和逻辑元件之间的路径中提供信号再生电路，从而隔离和升高信号。 这允许更快的切换操作。 提供路径，允许从水平导体到垂直导体的信号的选择性路由，而不通过逻辑元件。 而且，提供了一种路径，以允许水平导体被路由到多个垂直导体中的任何一个。

    Techniques for phase adjustment
    8.
    发明授权
    Techniques for phase adjustment 有权
    相位调整技术

    公开(公告)号：US08384460B1

    公开(公告)日：2013-02-26

    申请号：US13420349

    申请日：2012-03-14

    申请人： Chiakang Sung ,  John Henry Bui ,  Khai Nguyen ,  Bonnie I. Wang ,  Xiaobao Wang

    发明人： Chiakang Sung ,  John Henry Bui ,  Khai Nguyen ,  Bonnie I. Wang ,  Xiaobao Wang

    IPC分类号： H03H11/16

    CPC分类号： H03L7/0814 ,  H03K2005/00293

    摘要： An adjustable delay circuit includes first and second transistors each having a control input coupled to an input node of the adjustable delay circuit and an output coupled to an output node of the adjustable delay circuit. The adjustable delay circuit includes a first pass gate coupled between first and second capacitors and the output node of the adjustable delay circuit. The first and the second capacitors are coupled between a node at a high voltage and a node at a low voltage. The first pass gate is operable to be controlled by a first delay control signal.

    摘要翻译： 可调延迟电路包括第一和第二晶体管，每个晶体管具有耦合到可调延迟电路的输入节点的控制输入和耦合到可调延迟电路的输出节点的输出。 可调延迟电路包括耦合在第一和第二电容器之间的第一通过栅极和可调延迟电路的输出节点。 第一和第二电容器耦合在高电压节点和低电压节点之间。 第一通过门可操作以由第一延迟控制信号控制。

    Techniques for phase adjustment
    9.
    发明授权
    Techniques for phase adjustment 有权
    相位调整技术

    公开(公告)号：US08149038B1

    公开(公告)日：2012-04-03

    申请号：US12729114

    申请日：2010-03-22

    申请人： Chiakang Sung ,  John Henry Bui ,  Khai Nguyen ,  Bonnie I. Wang ,  Xiaobao Wang

    发明人： Chiakang Sung ,  John Henry Bui ,  Khai Nguyen ,  Bonnie I. Wang ,  Xiaobao Wang

    IPC分类号： H03H11/16

    CPC分类号： H03L7/0814 ,  H03K2005/00293

    摘要： A dynamic phase alignment circuit includes a phase generator circuit having delay-locked loop circuits that generate periodic output signals. Each of the delay-locked loop circuits generates one of the periodic output signals in response to at least two periodic input signals. A multiplexer circuit selects a selected periodic signal from among the periodic input signals and the periodic output signals based on select signals. A phase detection circuit compares a phase of the selected periodic signal to a data signal to generate a phase detection signal. A control logic circuit generates the select signals. The control logic circuit adjusts the select signals based on changes in the phase detection signal to cause the multiplexer circuit to adjust the phase of the selected periodic signal.

    摘要翻译： 动态相位对准电路包括具有产生周期性输出信号的延迟锁定环路电路的相位发生器电路。 每个延迟锁定环路电路响应于至少两个周期性输入信号产生周期性输出信号之一。 多路复用器电路基于选择信号从周期性输入信号和周期性输出信号中选择选定的周期信号。 相位检测电路将选择的周期信号的相位与数据信号进行比较，以产生相位检测信号。 控制逻辑电路产生选择信号。 控制逻辑电路基于相位检测信号的变化来调整选择信号，以使多路复用器电路调整所选周期信号的相位。