利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

210 条记录 (耗时 0.03 秒)

    Dynamic termination-impedance control for bidirectional I/O pins
    1.
    发明授权
    Dynamic termination-impedance control for bidirectional I/O pins 有权
    用于双向I / O引脚的动态终端阻抗控制

    公开(公告)号：US08854078B1

    公开(公告)日：2014-10-07

    申请号：US13223989

    申请日：2011-09-01

    申请人： Xiaobao Wang ,  Bonnie I. Wang ,  Chiakang Sung ,  Khai Q. Nguyen

    发明人： Xiaobao Wang ,  Bonnie I. Wang ,  Chiakang Sung ,  Khai Q. Nguyen

    IPC分类号： H03K17/16

    CPC分类号： H04L25/0298 ,  H04L25/0278

    摘要： Circuits, methods, and apparatus for dynamic control of source and termination impedances. One output stage provides a series termination when transmitting and a parallel termination when receiving data. A pull-up device has a nominal impedance of 50 ohms when the output stage pulls a pin from a low voltage to a high voltage, while a pull-down device has a nominal impedance of 50 ohms when the pin is pulled from a high voltage to a low voltage. Both the pull-up and pull-down devices are turned on when receiving data. Due to their non-linear current-voltage characteristics, the pull-up device appears as 50 ohms when the pin voltage is higher than one half the supply voltage, while the pull-down device appears as 50 ohms when the pin voltage is lower than one half the supply voltage. The pull-up and pull-down devices can be calibrated to provide a nominal 50 ohm impedance.

    摘要翻译： 用于动态控制源和端接阻抗的电路，方法和装置。 一个输出级在发送时提供串联终止，并在接收数据时提供并行终止。 当输出级将引脚从低电压拉到高电平时，上拉器件的标称阻抗为50欧姆，而当引脚从高电压拉出时，下拉器件的标称阻抗为50欧姆 到低电压。 上拉和下拉设备在接收数据时都打开。 由于其非线性电流 - 电压特性，当引脚电压高于电源电压的一半时，上拉器件显示为50欧姆，而当引脚电压低于50欧姆时，下拉器件显示为50欧姆 电源电压的一半。 可以校准上拉和下拉器件以提供标称的50欧姆阻抗。

    Dynamic termination-impedance control for bidirectional I/O pins
    2.
    发明授权
    Dynamic termination-impedance control for bidirectional I/O pins 有权
    用于双向I / O引脚的动态终端阻抗控制

    公开(公告)号：US08022723B1

    公开(公告)日：2011-09-20

    申请号：US11458675

    申请日：2006-07-19

    申请人： Xiaobao Wang ,  Bonnie I. Wang ,  Chiakang Sung ,  Khai Q. Nguyen

    发明人： Xiaobao Wang ,  Bonnie I. Wang ,  Chiakang Sung ,  Khai Q. Nguyen

    IPC分类号： H03K17/16

    CPC分类号： H04L25/0298 ,  H04L25/0278

    摘要： Circuits, methods, and apparatus for dynamic control of source and termination impedances. One output stage provides a series termination when transmitting and a parallel termination when receiving data. A pull-up device has a nominal impedance of 50 ohms when the output stage pulls a pin from a low voltage to a high voltage, while a pull-down device has a nominal impedance of 50 ohms when the pin is pulled from a high voltage to a low voltage. Both the pull-up and pull-down devices are turned on when receiving data. Due to their non-linear current-voltage characteristics, the pull-up device appears as 50 ohms when the pin voltage is higher than one half the supply voltage, while the pull-down device appears as 50 ohms when the pin voltage is lower than one half the supply voltage. The pull-up and pull-down devices can be calibrated to provide a nominal 50 ohm impedance.

    摘要翻译： 用于动态控制源和端接阻抗的电路，方法和装置。 一个输出级在发送时提供串联终止，并在接收数据时提供并行终止。 当输出级将引脚从低电压拉到高电平时，上拉器件的标称阻抗为50欧姆，而当引脚从高电压拉出时，下拉器件的标称阻抗为50欧姆 到低电压。 上拉和下拉设备在接收数据时都打开。 由于其非线性电流 - 电压特性，当引脚电压高于电源电压的一半时，上拉器件显示为50欧姆，而当引脚电压低于50欧姆时，下拉器件显示为50欧姆 电源电压的一半。 可以校准上拉和下拉器件以提供标称的50欧姆阻抗。

    On-chip termination with calibrated driver strength
    5.
    发明授权
    On-chip termination with calibrated driver strength 有权
    具有校准驱动器强度的片上终端

    公开(公告)号：US07221193B1

    公开(公告)日：2007-05-22

    申请号：US11040048

    申请日：2005-01-20

    申请人： Xiaobao Wang ,  Tzung-Chin Chang ,  Chiakang Sung ,  Khai Q. Nguyen

    发明人： Xiaobao Wang ,  Tzung-Chin Chang ,  Chiakang Sung ,  Khai Q. Nguyen

    IPC分类号： H03B1/00

    CPC分类号： H03K19/0005 ,  H04L25/0298

    摘要： Techniques are provided for controlling an on-chip termination resistance in an input or output (IO) buffer using calibration circuits. Each calibration circuit monitors the voltage between an external resistor and a group of on-chip transistors. When the effective resistance of the group of transistors matches the external resistance, the calibration circuit causes the effective resistance of drive transistors in the IO buffer to match the effective resistance of the group of on-chip transistors.

    摘要翻译： 提供了使用校准电路来控制输入或输出（IO）缓冲器中的片上终端电阻的技术。 每个校准电路监视外部电阻和片上晶体管组之间的电压。 当晶体组的有效电阻与外部电阻相匹配时，校准电路使得IO缓冲器中的驱动晶体管的有效电阻与片上晶体管组的有效电阻相匹配。

    Techniques for providing flexible on-chip termination control on integrated circuits
    6.
    发明授权
    Techniques for providing flexible on-chip termination control on integrated circuits 有权
    在集成电路上提供灵活的片上终端控制技术

    公开(公告)号：US07420386B2

    公开(公告)日：2008-09-02

    申请号：US11381356

    申请日：2006-05-02

    申请人： Xiaobao Wang ,  Chiakang Sung ,  Khai Q. Nguyen

    发明人： Xiaobao Wang ,  Chiakang Sung ,  Khai Q. Nguyen

    IPC分类号： H03K17/16

    CPC分类号： G11C7/1048 ,  G11C2207/2254 ,  H03H11/30 ,  H04L25/0278 ,  H04L25/0292

    摘要： On-chip termination (OCT) calibration techniques are provided that support input/output (IO) banks on an integrated circuit (IC) using OCT controllers. The OCT controllers calibrate the on-chip termination impedance in the IO banks using a shared parallel bus or separate parallel buses. Multiplexers or select logic in each IO bank select control signals from the OCT controllers in response to select signals. According to some embodiments, each of the IO banks on an IC can receive OCT control signals from any of the OCT controllers on the IC.

    摘要翻译： 提供使用OCT控制器在集成电路（IC）上支持输入/输出（IO）组的片上终止（OCT）校准技术。 OCT控制器使用共享并行总线或单独的并行总线校准IO组中的片上终端阻抗。 每个IO组中的多路复用器或选择逻辑根据选择信号选择来自OCT控制器的控制信号。 根据一些实施例，IC上的每个IO组可以从IC上的任何OCT控制器接收OCT控制信号。

    Techniques for providing adjustable on-chip termination impedance
    7.
    发明授权
    Techniques for providing adjustable on-chip termination impedance 有权
    提供可调节片上终端阻抗的技术

    公开(公告)号：US07417452B1

    公开(公告)日：2008-08-26

    申请号：US11462702

    申请日：2006-08-05

    申请人： Xiaobao Wang ,  Chiakang Sung ,  Khai Q. Nguyen ,  Sanjay K. Charagulla

    发明人： Xiaobao Wang ,  Chiakang Sung ,  Khai Q. Nguyen ,  Sanjay K. Charagulla

    IPC分类号： H03K17/16 ,  H03K19/003

    CPC分类号： H03K19/0005 ,  H03K17/005 ,  H03K17/145 ,  H03K17/6871 ,  H03K17/6872 ,  H03K17/693

    摘要： Techniques are provided for individually adjusting the on-chip termination impedance that is generated by input and output (IO) buffers in an input/output (IO) bank on an integrated circuit. The IO buffers in an IO bank can generate different on-chip termination impedances. And as a result, an IO bank can support more than one class of memory interfaces. An OCT calibration block generates a digital on-chip termination (OCT) calibration code. In some embodiments, circuitry in the IO banks can be configured to shift the OCT calibration code by one or more bits to adjust the series and/or parallel on-chip termination impedance in one or more IO buffers.

    摘要翻译： 提供了用于单独调整由集成电路中的输入/输出（IO）组中的输入和输出（IO）缓冲器产生的片上终端阻抗的技术。 IO bank中的IO缓冲区可以产生不同的片上终端阻抗。 因此，IO bank可以支持多个类别的内存接口。 OCT校准块产生数字片上终端（OCT）校准码。 在一些实施例中，IO组中的电路可被配置为将OCT校准码移位一个或多个位以调整一个或多个IO缓冲器中的串联和/或并行片上终端阻抗。

    Techniques for providing adjustable on-chip termination impedance
    8.
    发明授权
    Techniques for providing adjustable on-chip termination impedance 有权
    提供可调节片上终端阻抗的技术

    公开(公告)号：US07825682B1

    公开(公告)日：2010-11-02

    申请号：US12147403

    申请日：2008-06-26

    申请人： Xiaobao Wang ,  Chiakang Sung ,  Khai Q. Nguyen ,  Sanjay K. Charagulla

    发明人： Xiaobao Wang ,  Chiakang Sung ,  Khai Q. Nguyen ,  Sanjay K. Charagulla

    IPC分类号： H03K17/16 ,  H03K19/003

    CPC分类号： H03K19/0005 ,  H03K17/005 ,  H03K17/145 ,  H03K17/6871 ,  H03K17/6872 ,  H03K17/693

    摘要： Techniques are provided for individually adjusting the on-chip termination impedance that is generated by input and output (IO) buffers in an input/output (IO) bank on an integrated circuit. The IO buffers in an IO bank can generate different on-chip termination impedances. And as a result, an IO bank can support more than one class of memory interfaces. An OCT calibration block generates a digital on-chip termination (OCT) calibration code. In some embodiments, circuitry in the IO banks can be configured to shift the OCT calibration code by one or more bits to adjust the series and/or parallel on-chip termination impedance in one or more IO buffers.

    摘要翻译： 提供了用于单独调整由集成电路中的输入/输出（IO）组中的输入和输出（IO）缓冲器产生的片上终端阻抗的技术。 IO bank中的IO缓冲区可以产生不同的片上终端阻抗。 因此，IO bank可以支持多个类别的内存接口。 OCT校准块产生数字片上终端（OCT）校准码。 在一些实施例中，IO组中的电路可被配置为将OCT校准码移位一个或多个位以调整一个或多个IO缓冲器中的串联和/或并行片上终端阻抗。

    Techniques for controlling on-chip termination resistance using voltage range detection
    9.
    发明授权
    Techniques for controlling on-chip termination resistance using voltage range detection 有权
    使用电压范围检测控制片上终端电阻的技术

    公开(公告)号：US07218155B1

    公开(公告)日：2007-05-15

    申请号：US11040343

    申请日：2005-01-20

    申请人： Tzung-Chin Chang ,  Xiaobao Wang ,  Henry Kim ,  Chiakang Sung ,  Khai Q. Nguyen ,  Bonnie Wang ,  Jeffrey Tyhach ,  Gopinath Rangan

    发明人： Tzung-Chin Chang ,  Xiaobao Wang ,  Henry Kim ,  Chiakang Sung ,  Khai Q. Nguyen ,  Bonnie Wang ,  Jeffrey Tyhach ,  Gopinath Rangan

    IPC分类号： H03B1/00

    CPC分类号： H03K19/0005

    摘要： Techniques are provided for controlling an on-chip termination resistance in an input or output (IO) buffer using a calibration circuit. The calibration circuit monitors the voltage between an external resistor and a group of on-chip transistors. When voltage between the external resistor and the group of transistors is within a selected range, the calibration circuit causes the effective resistance of the transistors to match the resistance of the external resistor as closely as possible. The calibration circuit enables another set of transistors in the IO buffer so that the effective on resistance of the transistors in the IO buffer closely match the resistance of the external resistor.

    摘要翻译： 提供了使用校准电路控制输入或输出（IO）缓冲器中的片上终端电阻的技术。 校准电路监视外部电阻和片上晶体管组之间的电压。 当外部电阻和晶体管组之间的电压在选定范围内时，校准电路会使晶体管的有效电阻尽可能接近外部电阻的电阻。 校准电路使得IO缓冲器中的另一组晶体管能够使得IO缓冲器中的晶体管的有效导通电阻与外部电阻器的电阻紧密匹配。

    Self-compensating delay chain for multiple-date-rate interfaces
    10.
    发明授权
    Self-compensating delay chain for multiple-date-rate interfaces 有权
    多速率接口的自补偿延迟链

    公开(公告)号：US07200769B1

    公开(公告)日：2007-04-03

    申请号：US10037861

    申请日：2002-01-02

    申请人： Yan Chong ,  Chiakang Sung ,  Bonnie I. Wang ,  Joseph Huang ,  Xiaobao Wang ,  Philip Pan ,  Tzung-Chin Chang

    发明人： Yan Chong ,  Chiakang Sung ,  Bonnie I. Wang ,  Joseph Huang ,  Xiaobao Wang ,  Philip Pan ,  Tzung-Chin Chang

    IPC分类号： G06F1/04

    CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222 ,  G11C2207/108 ,  H03L7/0805 ,  H03L7/0814 ,  H03L7/091

    摘要： Methods and apparatus for delaying a clock signal for a multiple-data-rate interface. An apparatus provides an integrated circuit including a frequency divider configured to receive a first clock signal and a first variable-delay block configured to receive an output from the frequency divider. Also included is a phase detector configured to receive the first clock signal and an output from the first variable-delay block, and an up/down counter configured to receive an output from the phase detector. A second variable-delay block is configured to receive a second clock signal and a plurality of flip-flops are configured to receive an output from the second variable-delay block. The first variable-delay block and the second variable-delay block are configured to receive an output from the up/down counter.

    摘要翻译： 用于延迟多数据速率接口的时钟信号的方法和装置。 一种装置提供一种集成电路，其包括配置成接收第一时钟信号的分频器和被配置为接收来自分频器的输出的第一可变延迟块。 还包括相位检测器，被配置为接收第一时钟信号和来自第一可变延迟块的输出，以及配置为接收来自相位检测器的输出的上/下计数器。 第二可变延迟块被配置为接收第二时钟信号，并且多个触发器被配置为从第二可变延迟块接收输出。 第一可变延迟块和第二可变延迟块被配置为从加/减计数器接收输出。