公开(公告)号：US06603329B1

公开(公告)日：2003-08-05

申请号：US10044459

申请日：2002-01-11

申请人： Xiaobao Wang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen

发明人： Xiaobao Wang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen

IPC分类号： H03K1716

CPC分类号： H04L25/0278 ,  H04L25/0298

摘要： Techniques for on-chip impedance termination are provided that substantially reduce the number of external resistors that are need to provide impedance termination at a plurality of pairs of differential input/output (I/O) pins. On-chip impedance termination circuits of the present invention may include an amplifier, a feedback loop, and an impedance termination circuit. A reference voltage is provided to a first input terminal of the amplifier. A feedback loop is coupled between an output terminal of the amplifier and a second input terminal of the amplifier. The amplifier drives its output voltage so that the voltage at the second input terminal matches the voltage at the first input terminal. The output voltage of the amplifier determines the resistance of the impedance termination circuit. The impedance termination circuit is coupled between differential I/O pins.

摘要翻译： 提供用于片上阻抗终止的技术，其大大减少了需要在多对差分输入/输出（I / O）引脚上提供阻抗终端的外部电阻器的数量。 本发明的片上阻抗终端电路可以包括放大器，反馈回路和阻抗终端电路。 将参考电压提供给放大器的第一输入端。 反馈回路耦合在放大器的输出端和放大器的第二输入端之间。 放大器驱动其输出电压，使得第二输入端子处的电压与第一输入端子处的电压匹配。 放大器的输出电压决定了阻抗终端电路的电阻。 阻抗端接电路耦合在差分I / O引脚之间。

公开(公告)号：US06535031B1

公开(公告)日：2003-03-18

申请号：US10146438

申请日：2002-05-13

申请人： Khai Nguyen ,  Xiaobao Wang ,  In Whan Kim ,  Chiakang Sung ,  Richard G Cliff ,  Joseph Huang ,  Bonnie I Wang ,  Wayne Yeung

发明人： Khai Nguyen ,  Xiaobao Wang ,  In Whan Kim ,  Chiakang Sung ,  Richard G Cliff ,  Joseph Huang ,  Bonnie I Wang ,  Wayne Yeung

IPC分类号： H03K522

CPC分类号： H03K19/17744 ,  H03K19/018521 ,  H03K19/1778 ,  H03K19/17784

摘要： A programmable logic device is equipped for low voltage differential signaling (“LVDS”) by providing an LVDS input buffer and/or an LVDS output buffer on the device. I/O pins on the device that are used together in pairs for LVDS can alternatively be used individually for other types of signaling. The LVDS buffers are constructed to give good performance and to meet LVDS specifications despite variations due to temperature, manufacturing process inconsistency, and power supply changes.

公开(公告)号：US06384629B2

公开(公告)日：2002-05-07

申请号：US09738403

申请日：2000-12-15

申请人： Joseph Huang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen ,  Xiaobao Wang ,  Richard G. Cliff

发明人： Joseph Huang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen ,  Xiaobao Wang ,  Richard G. Cliff

IPC分类号： H01L2500

CPC分类号： H03K19/17736 ,  G01R31/318555 ,  G06F11/2273 ,  H03K19/17792

摘要： An improved interconnection between horizontal conductors and the input to logic elements. A signal regeneration circuit is provided in the path between the horizontal conductor and the logic element, thereby isolating and boosting the signal. This allows for faster switching operation. A path is provided allowing the selective routing of signals from the horizontal conductors to the vertical conductors, without passing through a logic element. Also, a path is provided to allow a horizontal conductors to be routed to any of a plurality of vertical conductors.

摘要翻译： 水平导体与逻辑元件输入之间的互连改善。 在水平导体和逻辑元件之间的路径中提供信号再生电路，从而隔离和升高信号。 这允许更快的切换操作。 提供路径，允许从水平导体到垂直导体的信号的选择性路由，而不通过逻辑元件。 而且，提供了一种路径，以允许水平导体被路由到多个垂直导体中的任何一个。

公开(公告)号：US08384460B1

公开(公告)日：2013-02-26

申请号：US13420349

申请日：2012-03-14

申请人： Chiakang Sung ,  John Henry Bui ,  Khai Nguyen ,  Bonnie I. Wang ,  Xiaobao Wang

发明人： Chiakang Sung ,  John Henry Bui ,  Khai Nguyen ,  Bonnie I. Wang ,  Xiaobao Wang

IPC分类号： H03H11/16

CPC分类号： H03L7/0814 ,  H03K2005/00293

摘要： An adjustable delay circuit includes first and second transistors each having a control input coupled to an input node of the adjustable delay circuit and an output coupled to an output node of the adjustable delay circuit. The adjustable delay circuit includes a first pass gate coupled between first and second capacitors and the output node of the adjustable delay circuit. The first and the second capacitors are coupled between a node at a high voltage and a node at a low voltage. The first pass gate is operable to be controlled by a first delay control signal.

摘要翻译： 可调延迟电路包括第一和第二晶体管，每个晶体管具有耦合到可调延迟电路的输入节点的控制输入和耦合到可调延迟电路的输出节点的输出。 可调延迟电路包括耦合在第一和第二电容器之间的第一通过栅极和可调延迟电路的输出节点。 第一和第二电容器耦合在高电压节点和低电压节点之间。 第一通过门可操作以由第一延迟控制信号控制。

公开(公告)号：US08149038B1

公开(公告)日：2012-04-03

申请号：US12729114

申请日：2010-03-22

申请人： Chiakang Sung ,  John Henry Bui ,  Khai Nguyen ,  Bonnie I. Wang ,  Xiaobao Wang

发明人： Chiakang Sung ,  John Henry Bui ,  Khai Nguyen ,  Bonnie I. Wang ,  Xiaobao Wang

IPC分类号： H03H11/16

CPC分类号： H03L7/0814 ,  H03K2005/00293

摘要： A dynamic phase alignment circuit includes a phase generator circuit having delay-locked loop circuits that generate periodic output signals. Each of the delay-locked loop circuits generates one of the periodic output signals in response to at least two periodic input signals. A multiplexer circuit selects a selected periodic signal from among the periodic input signals and the periodic output signals based on select signals. A phase detection circuit compares a phase of the selected periodic signal to a data signal to generate a phase detection signal. A control logic circuit generates the select signals. The control logic circuit adjusts the select signals based on changes in the phase detection signal to cause the multiplexer circuit to adjust the phase of the selected periodic signal.

摘要翻译： 动态相位对准电路包括具有产生周期性输出信号的延迟锁定环路电路的相位发生器电路。 每个延迟锁定环路电路响应于至少两个周期性输入信号产生周期性输出信号之一。 多路复用器电路基于选择信号从周期性输入信号和周期性输出信号中选择选定的周期信号。 相位检测电路将选择的周期信号的相位与数据信号进行比较，以产生相位检测信号。 控制逻辑电路产生选择信号。 控制逻辑电路基于相位检测信号的变化来调整选择信号，以使多路复用器电路调整所选周期信号的相位。

公开(公告)号：US06400598B1

公开(公告)日：2002-06-04

申请号：US09843299

申请日：2001-04-25

申请人： Khai Nguyen ,  Xiaobao Wang ,  In Whan Kim ,  Chiakang Sung ,  Richard G. Cliff ,  Joseph Huang ,  Bonnie I. Wang ,  Wayne Yeung

发明人： Khai Nguyen ,  Xiaobao Wang ,  In Whan Kim ,  Chiakang Sung ,  Richard G. Cliff ,  Joseph Huang ,  Bonnie I. Wang ,  Wayne Yeung

IPC分类号： G11C506

CPC分类号： H03K19/17744 ,  H03K19/018521 ,  H03K19/1778 ,  H03K19/17784

摘要： A programmable logic device is equipped for low voltage differential signaling (“LVDS”) by providing an LVDS input buffer and/or an LVDS output buffer on the device. I/O pins on the device that are used together in pairs for LVDS can alternatively be used individually for other types of signaling. The LVDS buffers are constructed to give good performance and to meet LVDS specifications despite variations due to temperature, manufacturing process inconsistency, and power supply changes.

摘要翻译： 可编程逻辑器件通过在器件上提供LVDS输入缓冲器和/或LVDS输出缓冲器来配备低电压差分信号（“LVDS”）。 对于LVDS成对使用的设备上的I / O引脚可以单独用于其他类型的信令。 尽管由于温度，制造过程不一致以及电源变化而导致变化，LVDS缓冲器也可以提供良好的性能和满足LVDS规范。

公开(公告)号：US06346827B1

公开(公告)日：2002-02-12

申请号：US09366937

申请日：1999-08-04

申请人： Wayne Yeung ,  Chiakang Sung ,  Myron W. Wong ,  Khai Nguyen ,  Bonnie I. Wang ,  Xiaobao Wang ,  Joseph Huang ,  In Whan Kim

发明人： Wayne Yeung ,  Chiakang Sung ,  Myron W. Wong ,  Khai Nguyen ,  Bonnie I. Wang ,  Xiaobao Wang ,  Joseph Huang ,  In Whan Kim

IPC分类号： H01L2500

CPC分类号： G11C5/147 ,  G11C5/066

摘要： A programmable input/output circuit for a programmable logic device input/output pin can be configured in a standard I/O mode, or in a reference voltage mode. The circuit includes a tristatable, but otherwise standard I/O buffer as well as a reference voltage clamp circuit. In reference voltage mode, the I/O circuit is tristated, and the reference voltage clamp circuit passes a reference voltage from the I/O pin to a reference voltage bus. In standard I/O mode, the I/O buffer is operational. The reference voltage clamp circuit isolates the I/O pin from the reference voltage bus and may include undervoltage and overvoltage protection to prevent disturbance of the reference voltage bus by an out-of-range I/O signal.

摘要翻译： 可编程逻辑器件输入/输出引脚的可编程输入/输出电路可以在标准I / O模式或参考电压模式下进行配置。 该电路包括可跟踪的标准I / O缓冲器以及参考电压钳位电路。 在参考电压模式下，I / O电路被三态化，参考电压钳位电路将参考电压从I / O引脚传递到参考电压总线。 在标准I / O模式下，I / O缓冲区可以运行。 参考电压钳位电路将I / O引脚与参考电压总线隔离，并可能包括欠压和过压保护，以防止参考电压总线受到超出范围I / O信号的干扰。

公开(公告)号：US08610462B1

公开(公告)日：2013-12-17

申请号：US13332730

申请日：2011-12-21

申请人： Xiaobao Wang ,  Chiakang Sung ,  Khai Nguyen ,  Bonnie I. Wang

发明人： Xiaobao Wang ,  Chiakang Sung ,  Khai Nguyen ,  Bonnie I. Wang

IPC分类号： H03K19/094 ,  H03K19/0175 ,  H03K3/00 ,  H03B1/00

CPC分类号： H03K3/356113

摘要： Circuits and techniques for operating an integrated circuit (IC) with a level shifter circuit are disclosed. A level shifter circuit with input and output terminals is operable to shift an input signal that ranges from a ground voltage to a first positive voltage to an output signal that ranges from the ground voltage to a second positive voltage. The level shifter circuit further includes a first kicker transistor having a first source-drain terminal operable to receive a buffered version of the input signal and having a second source-drain terminal coupled to the output terminal. The first kicker transistor may receive gate signals that turn on the first kicker transistor when the input signal is at the ground voltage and may pull the output terminal to the first positive voltage as the input signal transitions from the ground voltage to the first positive voltage.

摘要翻译： 公开了用于利用电平移位器电路来操作集成电路（IC）的电路和技术。 具有输入和输出端子的电平移位器电路可操作以将从地电压到第一正电压的输入信号移动到范围从接地电压到第二正电压的输出信号。 电平移位器电路还包括具有第一源极 - 漏极端子的第一汲取晶体管，第一源极 - 漏极端子可操作以接收缓冲版本的输入信号并具有耦合到输出端子的第二源极 - 漏极端子。 当输入信号处于接地电压时，第一icker晶体晶体管可以接收导通第一猝发晶体管的栅极信号，并且当输入信号从接地电压转变到第一正电压时，可以将输出端拉至第一正电压。

公开(公告)号：US07973553B1

公开(公告)日：2011-07-05

申请号：US12721759

申请日：2010-03-11

申请人： Xiaobao Wang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen ,  John Henry Bui

发明人： Xiaobao Wang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen ,  John Henry Bui

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H04L25/0278

摘要： A circuit includes first transistors and a comparator. The comparator compares a reference signal and a signal that is based on conductive states of the first transistors. A control circuit generates first control signals based on an output signal of the comparator. The conductive states of the first transistors are determined based on the first control signals. An arithmetic circuit performs an arithmetic function based on the first control signals and second control signals to generate calibration signals. Second transistors provide a termination impedance at an external terminal of the circuit that is based on the calibration signals.

摘要翻译： 电路包括第一晶体管和比较器。 比较器比较参考信号和基于第一晶体管的导电状态的信号。 控制电路根据比较器的输出信号产生第一控制信号。 基于第一控制信号来确定第一晶体管的导通状态。 算术电路基于第一控制信号和第二控制信号执行运算功能，以生成校准信号。 第二晶体管在基于校准信号的电路的外部端子处提供终端阻抗。

公开(公告)号：US07551014B1

公开(公告)日：2009-06-23

申请号：US11670109

申请日：2007-02-01

申请人： Bonnie I. Wang ,  Chiakang Sung ,  Khai Nguyen ,  Xiaobao Wang

发明人： Bonnie I. Wang ,  Chiakang Sung ,  Khai Nguyen ,  Xiaobao Wang

IPC分类号： G06F7/44

CPC分类号： H04L25/0272

摘要： Circuits and methods provide single-ended and differential signals. Single-ended drivers are used to, e.g., reduce pin capacitance. The output cell uses an inversion circuit, such as a phase splitter, to derive the differential signals from the same output signal and provide low skew between the differential signals at the output pins. Selection circuits are used to select between single-ended and differential output.

摘要翻译： 电路和方法提供单端和差分信号。 单端驱动器用于例如降低引脚电容。 输出单元使用诸如分相器的反相电路从相同的输出信号导出差分信号，并在输出引脚之间的差分信号之间提供低偏差。 选择电路用于在单端和差分输出之间进行选择。