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    SRAM Cell with Different Crystal Orientation than Associated Logic
    71.
    发明申请
    SRAM Cell with Different Crystal Orientation than Associated Logic 有权
    具有相关逻辑的不同晶体取向的SRAM单元

    公开(公告)号：US20100264465A1

    公开(公告)日：2010-10-21

    申请号：US12427416

    申请日：2009-04-21

    申请人： Theodore W. Houston

    发明人： Theodore W. Houston

    IPC分类号： H01L29/04 ,  H01L21/82

    CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/11 ,  H01L27/1207

    摘要： An integrated circuit containing logic transistors and an array of SRAM cells in which the logic transistors are formed in semiconductor material with one crystal orientation and the SRAM cells are formed in a second semiconductor layer with another crystal orientation. A process of forming an integrated circuit containing logic transistors and an array of SRAM cells in which the logic transistors are formed in a top semiconductor layer with one crystal orientation and the SRAM cells are formed in an epitaxial semiconductor layer with another crystal orientation. A process of forming an integrated circuit containing logic transistors and an array of SRAM cells in which the SRAM cells are formed in a top semiconductor layer with one crystal orientation and the logic transistors are formed in an epitaxial semiconductor layer with another crystal orientation.

    摘要翻译： 包含逻辑晶体管和SRAM单元阵列的集成电路，其中逻辑晶体管形成在具有一个晶体取向的半导体材料中，并且SRAM单元形成在具有另一晶体取向的第二半导体层中。 形成包含逻辑晶体管和SRAM单元阵列的集成电路的过程，其中逻辑晶体管形成在具有一个晶体取向的顶部半导体层中，并且SRAM单元形成在具有另一晶体取向的外延半导体层中。 形成包含逻辑晶体管的集成电路和SRAM单元的阵列的处理，其中SRAM单元形成在具有一个晶体取向的顶部半导体层中，并且逻辑晶体管形成在具有另一晶体取向的外延半导体层中。

    Integrated DRAM process/structure using contact pillars
    73.
    发明授权
    Integrated DRAM process/structure using contact pillars 有权
    集成DRAM工艺/结构使用接触柱

    公开(公告)号：US07745867B2

    公开(公告)日：2010-06-29

    申请号：US12042954

    申请日：2008-03-05

    申请人： Theodore W. Houston

    发明人： Theodore W. Houston

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10817 ,  H01L27/10811 ,  H01L27/10852 ,  H01L27/10855 ,  H01L28/91

    摘要： A capacitor under bitline DRAM memory cell and method for its fabrication provides a high density memory cell with the capacitor formed in the PMD layer. The memory cell utilizes several variations of storage contact pillar structures as, for example, a storage plate of the memory cell capacitor formed within a trench in the PMD layer. This capacitor plate structure is overlaid with a capacitor dielectric layer which is overlaid with another conductive layer, for example, the M1 layer to form the other capacitor plate. An access transistor formed between substrate active regions and a word line, is in electrical communication with a bit line contact, the storage contact capacitor plate, and the word line respectively. The high density memory cell benefits from the simple standard processes common to logic processes, and in one embodiment requiring only one additional masking step.

    摘要翻译： 位线DRAM存储单元下的电容器及其制造方法提供了在PMD层中形成的电容器的高密度存储单元。 存储单元利用多个存储接触柱结构的变型，例如形成在PMD层的沟槽内的存储单元电容器的存储板。 该电容器板结构覆盖有与另一个导电层（例如M1层）重叠的电容器电介质层，以形成另一个电容器板。 形成在衬底有源区和字线之间的存取晶体管分别与位线接触，存储接触电容器板和字线电连通。 高密度存储单元受益于逻辑过程通用的简单标准过程，并且在一个实施例中仅需要一个额外的掩蔽步骤。

    SRAM cell using separate read and write circuitry
    74.
    发明授权
    SRAM cell using separate read and write circuitry 有权
    SRAM单元使用单独的读写电路

    公开(公告)号：US07710763B2

    公开(公告)日：2010-05-04

    申请号：US12337258

    申请日：2008-12-17

    申请人： Theodore W. Houston

    发明人： Theodore W. Houston

    IPC分类号： G11C5/06 ,  G11C11/41

    CPC分类号： G11C11/413 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/412

    摘要： An SRAM device that includes an array of SRAM cells arranged in rows and columns. The SRAM device also includes a word line associated with at least one row, the word line operable to control access to cells in the row for both read and write. In addition, the SRAM device includes a write bit-line associated with at least one column operable to provide input to the cells in the column for write. Furthermore, the SRAM device includes a read bit-line associated with the column operable to receive output from cells in the column.

    摘要翻译： 一种SRAM器件，包括以行和列排列的SRAM单元阵列。 SRAM设备还包括与至少一行相关联的字线，该字线可操作以控制对行中的单元的访问以用于读取和写入。 此外，SRAM装置包括与至少一列相关联的写入位线，其可操作以向列中的单元提供输入用于写入。 此外，SRAM设备包括与列相关联的读位线，其可操作以接收列中的单元的输出。

    Method of fabricating etch-stopped SOI back-gate contact
    75.
    发明授权
    Method of fabricating etch-stopped SOI back-gate contact 有权
    制造蚀刻停止的SOI背栅极接触的方法

    公开(公告)号：US07534668B2

    公开(公告)日：2009-05-19

    申请号：US10417627

    申请日：2003-04-17

    申请人： Theodore W. Houston

    发明人： Theodore W. Houston

    IPC分类号： H01L21/84 ,  H01L21/00

    CPC分类号： H01L27/1203 ,  H01L21/31116

    摘要： The buried oxide region has a layer added which etches selectively with respect to oxide, allowing the contacts to a gate or to a back gate to be created without overetching into the buried oxide region.

    摘要翻译： 掩埋氧化物区域具有相对于氧化物选择性地蚀刻的层，允许在没有过蚀刻进入掩埋氧化物区域的情况下产生与栅极或后栅极的接触。

    INTEGRATED CIRCUIT HAVING SUPPLY VOLTAGE CONTROLLER
    76.
    发明申请
    INTEGRATED CIRCUIT HAVING SUPPLY VOLTAGE CONTROLLER 有权
    具有电源电压控制器的集成电路

    公开(公告)号：US20090109764A1

    公开(公告)日：2009-04-30

    申请号：US11930979

    申请日：2007-10-31

    申请人： Theodore W. Houston

    发明人： Theodore W. Houston

    IPC分类号： G11C5/14 ,  H02J1/00

    CPC分类号： G11C5/14 ,  G11C11/413

    摘要： An integrated circuit includes a supply voltage controller operable to receive a plurality of control signals and at least one circuit supply voltage and to output at least one variable supply voltage to at least one supply terminal of the integrated circuit The controller is operable to switch the variable supply voltage to a first voltage level when the control signals define a first operation and to a second voltage level different from the first voltage level when the control signals define a second operation. The controller is also operable to float the variable supply voltage to a third voltage level different from the first voltage level when the control signals define a third operation.

    摘要翻译： 集成电路包括电源电压控制器，其可操作以接收多个控制信号和至少一个电路电源电压，并将至少一个可变电源电压输出到集成电路的至少一个电源端。控制器可操作地切换变量 当控制信号限定第一操作时，将电压提供到第一电压电平，并在控制信号限定第二操作时将电压提供到与第一电压电平不同的第二电压电平。 当控制信号限定第三操作时，控制器还可操作以将可变电源电压浮动到与第一电压电平不同的第三电压电平。

    SRAM BIAS FOR READ AND WRITE
    77.
    发明申请
    SRAM BIAS FOR READ AND WRITE 有权
    SRAM读取和写入偏移

    公开(公告)号：US20090059685A1

    公开(公告)日：2009-03-05

    申请号：US11848442

    申请日：2007-08-31

    申请人： Theodore W. Houston

    发明人： Theodore W. Houston

    IPC分类号： G11C5/14

    CPC分类号： G11C5/14 ,  G11C11/413

    摘要： An integrated circuit includes a SRAM array including a plurality of SRAM cells arranged in a plurality of rows and columns and having a plurality of word lines and bit lines for accessing rows and columns of cells. A power supply controller has an input operable for receiving an operation signal indicative of whether the array is in a read or write operation. The power supply controller is operable to provide a variable low voltage for the array (VSSM) coupled to a low voltage supply terminal of the array. A level of the VSSM is based on the operation signal, wherein VSSM is at a lower level when in the read operation than when in the write operation. A high voltage supply for said array (VDDM) coupled to a high voltage supply terminal for the array is biased above a word line voltage (VWL) level in the read operation.

    摘要翻译： 一种集成电路包括一个SRAM阵列，它包括以多个行和列排列的多个SRAM单元，并且具有用于访问单元行和列的多个字线和位线。 电源控制器具有可操作用于接收指示阵列是处于读取还是写入操作的操作信号的输入。 电源控制器可操作地为耦合到阵列的低电压电源端子的阵列（VSSM）提供可变的低电压。 VSSM的电平基于操作信号，其中当在读取操作中VSSM处于比写入操作时更低的电平。 耦合到阵列的高电压电源端子的所述阵列（VDDM）的高压电源在读取操作中被偏置在字线电压（VWL）以上。

    SRAM cell using separate read and write circuitry
    78.
    发明授权
    SRAM cell using separate read and write circuitry 有权
    SRAM单元使用单独的读写电路

    公开(公告)号：US07483332B2

    公开(公告)日：2009-01-27

    申请号：US11202141

    申请日：2005-08-11

    申请人： Theodore W. Houston

    发明人： Theodore W. Houston

    IPC分类号： G11C8/16 ,  G11C8/14 ,  G11C11/41

    CPC分类号： G11C11/413 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/412

    摘要： The present invention provides circuitry for writing to and reading from an SRAM cell core, an SRAM cell, and an SRAM device. In one aspect, the circuitry includes a write circuit coupled to the SRAM cell core that includes at least one write transistor. The circuitry also includes a read circuit coupled to the SRAM cell core that includes at least one read transistor having a gate signal in common with the gate signal of the write transistor. The read transistor and the write transistor share a common gate signal, and each have an electrical characteristic, for which the electrical characteristic of the read transistor differs from that of the write transistor.

    摘要翻译： 本发明提供了用于向SRAM单元核，SRAM单元和SRAM器件进行写入和读取的电路。 在一个方面，电路包括耦合到SRAM单元芯的写入电路，其包括至少一个写入晶体管。 电路还包括耦合到SRAM单元芯的读取电路，其包括至少一个具有与写入晶体管的栅极信号共同的栅极信号的读取晶体管。 读取晶体管和写入晶体管共享公共栅极信号，并且每个具有电特性，读取晶体管的电特性与写入晶体管的电特性不同。

    SRAM CELL WITH ASYMMETRICAL TRANSISTORS FOR REDUCED LEAKAGE
    79.
    发明申请
    SRAM CELL WITH ASYMMETRICAL TRANSISTORS FOR REDUCED LEAKAGE 审中-公开
    具有不对称晶体管的SRAM单元，用于减少漏电

    公开(公告)号：US20080237745A1

    公开(公告)日：2008-10-02

    申请号：US12113770

    申请日：2008-05-01

    申请人： Shyh-Horng YANG ,  Kayvan SADRA ,  Theodore W. Houston

    发明人： Shyh-Horng YANG ,  Kayvan SADRA ,  Theodore W. Houston

    IPC分类号： H01L27/11

    CPC分类号： H01L27/1104 ,  H01L21/26586 ,  H01L27/0207 ,  H01L27/11 ,  H01L29/1045 ,  H01L29/66659

    摘要： A method of fabricating an SRAM cell with reduced leakage is disclosed. The method comprises fabricating asymmetrical transistors in the SRAM cell. The transistors are asymmetrical in a manner that reduces the drain leakage current of the transistors. The fabrication of asymmetrical pass transistors comprises forming a dielectric region on a surface of a substrate having a first conductivity type. A gate region having a length and a width is formed on the dielectric region. Source and drain extension regions having a second conductivity type are formed in the substrate on opposite sides of the gate region. A first pocket impurity region having a first concentration and the first conductivity type is formed adjacent the source. A second pocket impurity region having a second concentration and the first conductivity type may be formed adjacent the drain. If formed, the second concentration is smaller than the first concentration, reducing the gate induced drain leakage current.

    摘要翻译： 公开了一种制造具有减少泄漏的SRAM单元的方法。 该方法包括在SRAM单元中制造不对称晶体管。 晶体管以不减小晶体管的漏极漏电流的方式是不对称的。 不对称传输晶体管的制造包括在具有第一导电类型的衬底的表面上形成电介质区域。 在电介质区域上形成具有长度和宽度的栅极区域。 具有第二导电类型的源极和漏极延伸区域形成在栅极区域的相对侧上的衬底中。 在源附近形成具有第一浓度和第一导电类型的第一杂质杂质区。 可以在漏极附近形成具有第二浓度和第一导电类型的第二袋杂质区域。 如果形成，则第二浓度小于第一浓度，减小了栅极引起的漏极漏电流。

    SUB-LITHOGRAPHICS OPENING FOR BACK CONTACT OR BACK GATE
    80.
    发明申请
    SUB-LITHOGRAPHICS OPENING FOR BACK CONTACT OR BACK GATE 有权
    打开后接触或后盖的子图

    公开(公告)号：US20080166839A1

    公开(公告)日：2008-07-10

    申请号：US12034875

    申请日：2008-02-21

    申请人： Theodore W. Houston

    发明人： Theodore W. Houston

    IPC分类号： H01L21/336 ,  H01L21/28

    CPC分类号： H01L27/1203 ,  H01L21/76816

    摘要： A low resistance buried back contact for SOI devices. A trench is etched in an insulating layer at minimum lithographic dimension, and sidewalls are deposited in the trench to decrease its width to sublithographic dimension. Conducting material is deposited in the trench, which serves as a low-resistance contact to the back side of the device. In another embodiment, the trench-fill material is separated from the device by an insulating layer, and serves as a back gate structure.

    摘要翻译： SOI器件的低电阻埋后接触。 在最小光刻尺寸的绝缘层中蚀刻沟槽，并且在沟槽中沉积侧壁以将其宽度减小到亚光刻尺寸。 导电材料沉积在沟槽中，其用作与器件背面的低电阻接触。 在另一个实施例中，沟槽填充材料通过绝缘层与器件分离，并且用作背栅结构。