公开(公告)号：US11728354B2

公开(公告)日：2023-08-15

申请号：US17893247

申请日：2022-08-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takeshi Aoki ,  Yoshiyuki Kurokawa ,  Takayuki Ikeda ,  Hikaru Tamura

IPC: H01L27/146 ,  G09G3/36 ,  H01L29/786

CPC classification number: H01L27/14603 ,  G09G3/3648 ,  H01L27/14612 ,  H01L27/14616 ,  H01L27/14625 ,  H01L27/14636 ,  H01L27/14641 ,  H01L27/14643 ,  H01L29/7869 ,  G09G2354/00

Abstract: An object is to provide a pixel structure of a display device including a photosensor which prevents changes in an output of the photosensor and a decrease in imaging quality. The display device has a pixel layout structure in which a shielding wire is disposed between an FD and an imaging signal line (a PR line, a TX line, or an SE line) or between the FD and an image-display signal line in order to reduce or eliminate parasitic capacitance between the FD and a signal line for the purpose of suppressing changes in the potential of the FD. An imaging power supply line, image-display power supply line, a GND line, a common line, or the like whose potential is fixed, such as a common potential line, is used as a shielding wire.

公开(公告)号：US11710751B2

公开(公告)日：2023-07-25

申请号：US17490009

申请日：2021-09-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki Kurokawa ,  Takayuki Ikeda ,  Hikaru Tamura ,  Munehiro Kozuma ,  Masataka Ikeda ,  Takeshi Aoki

IPC: H01L27/146 ,  H01L29/786 ,  H01L31/105 ,  H04N25/63 ,  H04N25/75 ,  H04N25/76

CPC classification number: H01L27/14616 ,  H01L27/14603 ,  H01L27/14636 ,  H01L27/14643 ,  H01L29/7869 ,  H01L31/1055 ,  H04N25/63 ,  H04N25/75 ,  H04N25/76 ,  H01L27/14632

Abstract: In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.

公开(公告)号：US11568223B2

公开(公告)日：2023-01-31

申请号：US16604363

申请日：2018-04-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuki Okamoto ,  Munehiro Kozuma ,  Yoshiyuki Kurokawa ,  Takayuki Ikeda

IPC: G06F7/50 ,  G06F7/523 ,  G06F7/57 ,  G06F7/544 ,  G06N3/063

Abstract: A neural network circuit having a novel structure is provided.
A plurality of arithmetic circuits each including a register, a memory, a multiplier circuit, and an adder circuit are provided. The memory outputs different weight data in response to switching of a context signal. The multiplier circuit outputs multiplication data of the weight data and input data held in the register. The adder circuit performs a product-sum operation by adding the obtained multiplication data to data obtained by a product-sum operation in an adder circuit of another arithmetic circuit. The obtained product-sum operation data is output to an adder circuit of another arithmetic circuit, so that product-sum operations of different weight data and input data are performed.

公开(公告)号：US11509918B2

公开(公告)日：2022-11-22

申请号：US16466693

申请日：2018-01-16

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yoshiyuki Kurokawa

IPC: H04N19/42 ,  G06T9/00 ,  G09G3/36

Abstract: A semiconductor device and electronic device with reduced power consumption are provided. The semiconductor device includes an encoder, a decoder, and a source driver circuit. An output terminal of the encoder is electrically connected to an input terminal of the source driver circuit, and an output terminal of the source driver circuit is electrically connected to an input terminal of the decoder. The encoder converts input image data into feature-extracted image data, and the decoder restores the feature-extracted image data to the original image data. In addition, provision of a circuit that performs convolution processing using a weight filter for the encoder enables calculation using a convolutional neural network.

公开(公告)号：US11501675B2

公开(公告)日：2022-11-15

申请号：US16705657

申请日：2019-12-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Yoshiyuki Kurokawa

IPC: G09G3/3225 ,  G09G3/00 ,  B60K35/00 ,  G09G5/14

Abstract: A display system and vehicle that have novel structures are provided. The display system includes a display panel, a correction circuit, and a memory circuit. The display panel is flexible. The display panel includes a display region and a non-display region. The memory circuit has a function of storing first data about the display region and second data about the non-display region. The non-display region has a region which overlaps with the display region when the display panel is bent. The correction circuit has a function of generating image data to be written to pixels in the display region on the basis of the first data and the second data.

公开(公告)号：US11430311B2

公开(公告)日：2022-08-30

申请号：US16727987

申请日：2019-12-27

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yoshiyuki Kurokawa

IPC: H04N5/3745 ,  G08B13/196 ,  H04N5/232 ,  H04N5/378

Abstract: An imaging device capable of detecting differences with low power consumption is provided. The imaging device includes a pixel including a photoelectric conversion element and a transistor; an analog processing circuit; and a digital processing circuit. The imaging device is operated in a first mode and a second mode. In the first mode, the analog processing circuit detects a difference between first imaging data taken by the pixel and second imaging data taken by the pixel and generates a trigger signal on the basis of the value of the difference. In the second mode, the digital processing circuit converts third imaging data taken by the pixel into digital data. Switching from the first mode to the second mode is performed on the basis of the trigger signal.

公开(公告)号：US11417704B2

公开(公告)日：2022-08-16

申请号：US17278675

申请日：2019-10-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hajime Kimura ,  Yoshiyuki Kurokawa

IPC: H01L27/22 ,  H01L27/24 ,  H03K19/20

Abstract: A semiconductor device that can perform product-sum operation with low power consumption is provided. The semiconductor device includes first and second circuits; the first circuit includes a first holding node and the second circuit includes a second holding node. The first circuit is electrically connected to first and second input wirings and first and second wirings, the second circuit is electrically connected to the first and second input wirings and the first and second wirings, and the first and second circuits each have a function of holding first and second potentials corresponding to first data at the first and second holding nodes. When a potential corresponding to second data is input to each of the first and second input wirings, the first circuit outputs a current to one of the first wiring and the second wiring and the second circuit outputs a current to the other of the first wiring and the second wiring. The currents output from the first and second circuits to the first wiring or the second wiring are determined in accordance with the first and second potentials held at the first and second holding nodes.

公开(公告)号：US11314484B2

公开(公告)日：2022-04-26

申请号：US16609902

申请日：2018-05-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Munehiro Kozuma ,  Takeshi Aoki ,  Seiichi Yoneda ,  Yoshiyuki Kurokawa

IPC: G06F7/544 ,  G06N3/063

Abstract: A semiconductor device having a novel structure is provided.
The semiconductor device includes a plurality of operation circuits that can switch different kinds of operation processing; a plurality of switch circuits that can switch a connection state between the operation circuits; and a controller. The operation circuit includes a first memory that stores data corresponding to a weight parameter used in the plurality of kinds of operation processing. The operation circuit executes a product-sum operation by switching weight data in accordance with a context. The switch circuit includes a second memory that stores data for switching a plurality of connection states in response to switching of a second context signal. The controller generates a second context signal on the basis of a first context signal. The amount of data stored in the second memory can be smaller than the amount of data stored in the first memory in the operation circuit.

公开(公告)号：US11264973B2

公开(公告)日：2022-03-01

申请号：US17113763

申请日：2020-12-07

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hajime Kimura ,  Yoshiyuki Kurokawa

IPC: H03K3/037 ,  G06N3/04 ,  G11C11/16 ,  G11C13/00

Abstract: A semiconductor device capable of performing product-sum operation with low power consumption. The semiconductor device includes first and second logic circuits, first to fourth transistors, and first and second holding units. A low power supply potential input terminal of the first logic circuit is electrically connected to the first and third transistors. A low power supply potential input terminal of the second logic circuit is electrically connected to the second and fourth transistors. The potentials of second gates of the first and fourth transistors are held in the first holding unit as potentials corresponding to first data. The potentials of second gates of the second and third transistors are held in the second holding unit. The on/off states of the first to fourth transistors are determined by second data. A difference in signal input/output time between the first and second logic circuits depends on the first data and the second data.

公开(公告)号：US11232831B2

公开(公告)日：2022-01-25

申请号：US16508939

申请日：2019-07-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki Kurokawa

IPC: G11C11/4093 ,  H04N5/38 ,  H04N5/44 ,  H01L27/146 ,  H01L21/00 ,  H04N21/426 ,  H04N5/40 ,  H04N5/455

Abstract: A semiconductor device including cells arranged in a matrix with m rows and n columns, where each of m and n is an integer of 2 or more, in which the cells retain first data with m rows and n columns, the cells input second data with m rows, and the semiconductor device outputs third data with m rows obtained by vector-matrix multiplication of the first data and the second data, is provided.