公开(公告)号：US6080661A

公开(公告)日：2000-06-27

申请号：US87441

申请日：1998-05-29

Applicant: Subhas Bothra

Inventor： Subhas Bothra

IPC: H01L21/60 ,  H01L21/4763

CPC classification number: H01L21/76897

Abstract: Disclosed are methods for making reliable conductive vias in semiconductor devices that are fabricated over a semiconductor wafer. The semiconductor device includes a plurality of transistor devices having diffusion regions and polysilicon gate electrodes, and an oxide material that covers a top surface of the polysilicon gate electrodes of the transistor devices. A silicon nitride layer is also disposed over the semiconductor devices and a dielectric layer is disposed over the silicon nitride layer. The method includes depositing a silicon nitride layer over the dielectric layer, and etching nitride windows in the silicon nitride layer to expose the dielectric layer where conductive contacts to selected polysilicon gate electrodes are desired. The method then includes pattering a photoresist mask over the silicon nitride layer. The photoresist mask is configured to have a plurality of windows defining all contacts to both selected ones of the diffusion regions and selected ones of the polysilicon gate electrodes, and some of the plurality of windows are defined over the nitride windows. Furthermore, the method includes performing a series of dielectric and silicon nitride etch operations to substantially simultaneously form via holes down to selected polysilicon gate electrodes and selected diffusion regions. Once the via holes are etched, a suitable conductive contact fill process may be performed.

Abstract translation: 公开了在半导体晶片上制造的半导体器件中制造可靠的导电通孔的方法。 半导体器件包括具有扩散区域和多晶硅栅电极的多个晶体管器件和覆盖晶体管器件的多晶硅栅电极的顶表面的氧化物材料。 氮化硅层也设置在半导体器件上方，并且介电层设置在氮化硅层上。 该方法包括在电介质层上沉积氮化硅层，以及蚀刻氮化硅层中的氮化物窗口以暴露需要与所选择的多晶硅栅电极的导电接触的电介质层。 该方法然后包括在氮化硅层上图案化光致抗蚀剂掩模。 光致抗蚀剂掩模被配置为具有多个窗口，其限定了所选择的扩散区域中的所选择的一个以及多晶硅栅极电极中的所选择的多个栅电极的所有触点，并且多个窗口中的一些限定在氮化物窗口上。 此外，该方法包括执行一系列电介质和氮化硅蚀刻操作，以基本上同时形成向下选定的多晶硅栅电极和选定扩散区的通孔。 一旦通孔被蚀刻，就可以执行合适的导电接触填充过程。

公开(公告)号：US6034434A

公开(公告)日：2000-03-07

申请号：US024967

申请日：1998-02-06

Applicant: Subhas Bothra ,  Milind G. Weling

Inventor： Subhas Bothra ,  Milind G. Weling

IPC: H01L21/3105 ,  H01L21/768 ,  H01L23/522 ,  H01L23/52

CPC classification number: H01L21/31053 ,  H01L21/76819 ,  H01L21/76837 ,  H01L23/522 ,  H01L2924/0002

Abstract: A method of forming sharp oxide peaks on the surface of a semiconductor wafer for the purpose of conditioning polishing pads used during a Chemical Mechanical Polishing process is disclosed. In order to create oxide peaks on the surface of a wafer, additional elements are added to a trace layer of the wafer. An oxide layer is deposited over the additional elements using an Electron Cyclotron Resonance Chemical Vapor Deposition process, which includes a sputtering step, in order to create sharp peaks in the oxide layer over the additional lines. In some embodiments, the additional elements may be formed from a multiplicity of rectangular blocks over which pyramid-like oxide peaks are created. In others, they may be formed from a multiplicity of rectangular blocks connected by narrow lines over which pyramid-like oxide peaks and knife-edged peaks, respectively, are created.

Abstract translation: 公开了一种在化学机械研磨过程中用于调节抛光垫的目的，在半导体晶片的表面上形成尖锐的氧化物峰的方法。 为了在晶片的表面上产生氧化物峰，将另外的元素添加到晶片的迹线层。 使用电子回旋加速器共振化学气相沉积工艺在附加元件上沉积氧化物层，其包括溅射步骤，以便在附加管线上的氧化物层中产生尖锐的峰。 在一些实施例中，附加元件可以由多个矩形块形成，在其上形成金字塔状氧化物峰。 在另一些实施例中，它们可以由多个矩形块形成，该矩形块通过分别形成有金字塔形氧化物峰和刀刃峰的窄线连接。

公开(公告)号：US5985749A

公开(公告)日：1999-11-16

申请号：US881614

申请日：1997-06-25

Applicant: Xi-Wei Lin ,  Subhas Bothra

Inventor： Xi-Wei Lin ,  Subhas Bothra

IPC: H01L21/768 ,  H01L21/28

CPC classification number: H01L21/76843

Abstract: The invention relates to integrated circuits and to via hole structures which include a tungsten silicide barrier layer and to methods of forming such via hole structures. In an exemplary embodiment, a metal layer is formed on a sidewall and a bottom surface of the via hole, a WSi.sub.x barrier layer is formed on the first metal layer by chemical vapor deposition and the via hole is subsequently filled with a metal. The tungsten silicide barrier layer effectively suppresses device degradation resulting from the release of gaseous species from the sidewall of the via hole during plug formation. Semiconductor devices can thus be fabricated which are immune or less susceptible to metal open failures due to incomplete via filling.

Abstract translation: 本发明涉及集成电路和包括硅化钨阻挡层的通孔结构以及形成这种通孔结构的方法。 在一个示例性实施例中，在通孔的侧壁和底表面上形成金属层，通过化学气相沉积在第一金属层上形成WSix阻挡层，随后填充金属孔。 硅化钨阻挡层有效地抑制了在插塞形成期间从气孔物质从通孔的侧壁释放出来的装置劣化。 因此可以制造半导体器件，其由于不完全的通孔填充而免疫或不易受金属开路故障的影响。

公开(公告)号：US5889389A

公开(公告)日：1999-03-30

申请号：US14832

申请日：1998-01-28

Applicant: Subhas Bothra ,  Jayarama N. Shenoy

Inventor： Subhas Bothra ,  Jayarama N. Shenoy

IPC: H01G5/013 ,  H01M10/46

CPC classification number: H01G5/0138

Abstract: The present invention is a micro-electromechanical voltage shifter. According to one embodiment, the voltage shifter of the present invention comprises a capacitor and micro-electromechanical means for changing a capacitance of the capacitor. The capacitor is initially charged and then electrically isolated. When the capacitance is altered, potential difference across the capacitor is shifted accordingly. In one embodiment of the present invention, the micro-electromechanical means includes a gear wheel driven by a micro-motor. The gear wheel preferably includes a plurality of teeth protruding along a circumference of the gear wheel. Further, the gear wheel is positioned next to the capacitor and configured to move the teeth into and out of a gap between the capacitor plates. As the teeth is preferably made of dielectric material, the voltage across the capacitor is changed as a tooth enters or leaves the gap. In another embodiment, the teeth may be made of a conducting material. The thickness of the teeth may also vary to provide a wide range of voltage levels.

Abstract translation: 本发明是一种微机电电压转换器。 根据一个实施例，本发明的电压转换器包括用于改变电容器的电容的电容器和微机电装置。 电容器最初被充电然后被电隔离。 当电容变化时，电容器两端的电位差相应地移动。 在本发明的一个实施例中，微机电装置包括由微型电动机驱动的齿轮。 齿轮优选地包括沿着齿轮的圆周突出的多个齿。 此外，齿轮位于电容器旁边并且被配置成将齿移入和移出电容器板之间的间隙。 由于齿优选由介电材料制成，所以当齿进入或离开间隙时，电容器两端的电压发生变化。 在另一个实施例中，齿可以由导电材料制成。 齿的厚度也可以改变以提供宽范围的电压水平。

公开(公告)号：US5854510A

公开(公告)日：1998-12-29

申请号：US883403

申请日：1997-06-26

Applicant: Harlan Lee Sur, Jr. ,  Subhas Bothra ,  Xi-Wei Lin ,  Martin H. Manley ,  Robert Payne

Inventor： Harlan Lee Sur, Jr. ,  Subhas Bothra ,  Xi-Wei Lin ,  Martin H. Manley ,  Robert Payne

IPC: H01C13/00 ,  H01L21/822 ,  H01L23/525 ,  H01L27/04 ,  H01L27/10 ,  H01L29/00

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/3011

Abstract: Disclosed is a semiconductor fuse structure having a low power programming threshold and anti-reverse engineering characteristics. The fuse structure includes a substrate having a field oxide region. A polysilicon strip that has an increased dopant concentration region lies over the field oxide region. The fuse structure further includes a silicided metallization layer having first and second regions lying over the polysilicon strip. The first region has a first thickness, and the second region has a second thickness that is less than the first thickness and is positioned substantially over the increased dopant concentration region of the polysilicon strip. Preferably, the first region of the silicided metallization layer has a first side and a second side located on opposite sides of the second region, and the resulting fuse structure is substantially rectangular in shape. Therefore, the semiconductor fuse structure can be programmed by breaking the second region.

Abstract translation: 公开了具有低功率编程阈值和抗逆向工程特性的半导体熔丝结构。 熔丝结构包括具有场氧化物区域的衬底。 具有增加的掺杂剂浓度区域的多晶硅条带位于场氧化物区域之上。 熔丝结构还包括具有位于多晶硅条上的第一和第二区域的硅化金属化层。 第一区域具有第一厚度，并且第二区域具有小于第一厚度的第二厚度，并且基本上位于多晶硅条的增加的掺杂剂浓度区域之上。 优选地，硅化金属化层的第一区域具有位于第二区域的相对侧上的第一侧和第二侧，并且所得到的熔丝结构的形状基本上是矩形。 因此，可以通过断开第二区域来编程半导体熔丝结构。

公开(公告)号：US5639697A

公开(公告)日：1997-06-17

申请号：US593900

申请日：1996-01-30

Applicant: Milind G. Weling ,  Subhas Bothra ,  Calvin T. Gabriel

Inventor： Milind G. Weling ,  Subhas Bothra ,  Calvin T. Gabriel

IPC: H01L21/3105 ,  H01L21/302 ,  H01L21/463

CPC classification number: H01L21/31053 ,  Y10S438/926

Abstract: A method of commonizing the pattern density of topography for different layers of semiconductor wafers to improve the Chemical Mechanical Polishing process used during wafer processing is disclosed. In order to achieve a predetermined pattern density of topography on the surface of a wafer, dummy raised lines are inserted as necessary into gaps between active conductive traces on a trace layer. In some embodiments, the predetermined pattern density is in the range of approximately 40% to 80%. In some applications, both the active conductive traces and the dummy raised lines are formed from a metallic material that is deposited in one single step with an insulating layer deposited over both the active conductive traces and the dummy raised lines prior to the Chemical Mechanical Polishing process. In other applications, the dummy raised lines are formed from the insulating layer.

Abstract translation: 公开了用于不同层的半导体晶片的形貌图案密度的方法，以改进在晶片处理期间使用的化学机械抛光工艺。 为了实现晶片表面上的预定图案形状密度，根据需要将虚拟凸起线插入到迹线层上的有源导电迹线之间的间隙中。 在一些实施例中，预定图案密度在大约40％至80％的范围内。 在一些应用中，活性导电迹线和虚拟凸起线都由金属材料形成，该金属材料在化学机械抛光过程之前在一个步骤中沉积，绝缘层沉积在两个有源导电迹线和虚拟凸起线上 。 在其他应用中，假凸起线由绝缘层形成。

公开(公告)号：US08270629B2

公开(公告)日：2012-09-18

申请号：US11256166

申请日：2005-10-24

Applicant: Subhas Bothra ,  Louis Pandula

Inventor： Subhas Bothra ,  Louis Pandula

IPC: H04R1/10

CPC classification number: H04M1/6058 ,  H04M1/6066 ,  H04M1/72569 ,  H04R5/033 ,  H04R2201/107 ,  H04R2420/01 ,  H04R2420/07 ,  H04R2499/11

Abstract: A system and method allow for safe use of headphones that include a microphone when using the headphones with a cellular phone, a music device, or the like. A desired audio signal, e.g., a voice of a caller or music, is discontinued when a microphone associated with the headphones picks up either a change in ambient noise or a particular type of ambient noise, e.g., an ambulance, a police car, a fire truck, someone yelling, brakes squealing, or the like. During this state, the headphones output either an audible alert signal, the ambient noise, or a pre-stored signal that states “fire,” “police,”, “yelling,” etc. In this way, a person can safely talk on the phone or listen to music when walking or driving, while still being cognizant of what is going on around them.

Abstract translation: 一种系统和方法允许在使用具有蜂窝电话的耳机，音乐设备等时安全地使用包括麦克风的耳机。 当与耳机相关联的麦克风拾取环境噪声的变化或特定类型的环境噪声时，例如救护车，警车，警车等的呼叫者或音乐的所需音频信号，例如呼叫者或音乐的语音， 消防车，有人大喊大叫，刹车尖叫等等。 在这种状态下，耳机输出声音报警信号，环境噪声或预先存储的“火灾”，“警察”，“大喊大叫”等信号。以这种方式，一个人可以安全地说话 在走路或驾驶时，电话或听音乐，同时仍然认识到他们周围发生了什么。

公开(公告)号：US07911310B2

公开(公告)日：2011-03-22

申请号：US12360068

申请日：2009-01-26

Applicant: Carol Barrett ,  Tom McKay ,  Subhas Bothra

Inventor： Carol Barrett ,  Tom McKay ,  Subhas Bothra

IPC: H01F5/00

CPC classification number: H01L23/5227 ,  H01F2017/0046 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An inductor circuit is disclosed. The inductor circuit includes a first in-silicon inductor and a second in-silicon inductor each having multiple turns. A portion of the multiple turns of the second in-silicon inductor is formed between turns of the first in-silicon inductor. The first and second in-silicon inductors are configured such that a differential current flowing through the first in-silicon inductor and the second in-silicon inductor flows in a same direction in corresponding turns of inductors.

Abstract translation: 公开了一种电感器电路。 电感器电路包括第一硅芯片电感器和第二硅芯片电感器，每个具有多个匝数。 第二硅电感器的多圈的一部分形成在第一硅内感应器的匝之间。 第一和第二硅内电感器被配置为使得流过第一硅芯片电感器和第二硅芯片电感器的差分电流在相应的电感圈中以相同的方向流动。

公开(公告)号：US07434189B2

公开(公告)日：2008-10-07

申请号：US11254903

申请日：2005-10-20

Applicant: Donald Baumann ,  Subhas Bothra

Inventor： Donald Baumann ,  Subhas Bothra

IPC: G06F17/50

CPC classification number: H01L27/0203 ,  H01L23/5286 ,  H01L24/06 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/00

Abstract: Embodiments of the present invention provide an integrated circuit (IC) in which power to input output (IO) drivers may be distributed within unused areas over macro processing circuits. This IC includes a long distance power and ground distribution network, an input output (IO) power and ground distribution network, a number of macro processing circuits, and IO circuits. The long distance power and ground distribution network electrically couples to the IO power and ground distribution network. Both the power and ground distribution networks may be located within the upper level conductive layers. IO power and ground distribution network locally supplies power and ground to IO circuits. Macro processing circuits may be located beneath the power distribution network as some macro processing circuits do not require access to upper level conductive layers. By placing these macro processing circuits beneath these power distribution networks, die size may be reduced.

Abstract translation: 本发明的实施例提供一种集成电路（IC），其中输入输出（IO）驱动器的功率可以通过宏处理电路分布在未使用的区域内。 该IC包括长距离电源和地面分配网络，输入输出（IO）电源和地面分配网络，多个宏处理电路和IO电路。 长距离电力和地面分配网络电耦合到IO电力和地面分配网络。 电力和地面分布网络都可以位于上层导电层内。 IO电源和地面分配网络本地为IO电路供电和接地。 宏处理电路可以位于配电网下方，因为一些宏处理电路不需要访问上层导电层。 通过将这些宏处理电路放置在这些配电网络的下方，可以减小管芯尺寸。

公开(公告)号：US20070090401A1

公开(公告)日：2007-04-26

申请号：US11254903

申请日：2005-10-20

Applicant: Donald Baumann ,  Subhas Bothra

Inventor： Donald Baumann ,  Subhas Bothra

IPC: H01L27/10

CPC classification number: H01L27/0203 ,  H01L23/5286 ,  H01L24/06 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/00

Abstract: Embodiments of the present invention provide an integrated circuit (IC) in which power to input output (IO) drivers may be distributed within unused areas over macro processing circuits. This IC includes a long distance power and ground distribution network, an input output (IO) power and ground distribution network, a number of macro processing circuits, and IO circuits. The long distance power and ground distribution network electrically couples to the IO power and ground distribution network. Both the power and ground distribution networks may be located within the upper level conductive layers. IO power and ground distribution network locally supplies power and ground to IO circuits. Macro processing circuits may be located beneath the power distribution network as some macro processing circuits do not require access to upper level conductive layers. By placing these macro processing circuits beneath these power distribution networks, die size may be reduced.

Abstract translation: 本发明的实施例提供一种集成电路（IC），其中输入输出（IO）驱动器的功率可以通过宏处理电路分布在未使用的区域内。 该IC包括长距离电源和地面分配网络，输入输出（IO）电源和地面分配网络，多个宏处理电路和IO电路。 长距离电力和地面分配网络电耦合到IO电力和地面分配网络。 电力和地面分布网络都可以位于上层导电层内。 IO电源和地面分配网络本地为IO电路供电和接地。 宏处理电路可以位于配电网下方，因为一些宏处理电路不需要访问上层导电层。 通过将这些宏处理电路放置在这些配电网络的下方，可以减小管芯尺寸。