公开(公告)号：US5882998A

公开(公告)日：1999-03-16

申请号：US55018

申请日：1998-04-03

申请人： Harlan Lee Sur, Jr. ,  Subhas Bothra ,  Xi-Wei Lin ,  Martin H. Manley ,  Robert Payne

发明人： Harlan Lee Sur, Jr. ,  Subhas Bothra ,  Xi-Wei Lin ,  Martin H. Manley ,  Robert Payne

IPC分类号： H01C13/00 ,  H01L21/822 ,  H01L23/525 ,  H01L27/04 ,  H01L29/00

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/3011

摘要： Disclosed is a semiconductor fuse structure having a low power programming threshold and anti-reverse engineering characteristics. The fuse structure includes a substrate having a field oxide region. A polysilicon strip that has an increased dopant concentration region lies over the field oxide region. The fuse structure further includes a silicided metallization layer having first and second regions lying over the polysilicon strip. The first region has a first thickness, and the second region has a second thickness that is less than the first thickness and is positioned substantially over the increased dopant concentration region of the polysilicon strip. Preferably, the first region of the silicided metallization layer has a first side and a second side located on opposite sides of the second region, and the resulting fuse structure is substantially rectangular in shape. Therefore, the semiconductor fuse structure can be programmed by breaking the second region.

摘要翻译： 公开了具有低功率编程阈值和抗逆向工程特性的半导体熔丝结构。 熔丝结构包括具有场氧化物区域的衬底。 具有增加的掺杂剂浓度区域的多晶硅条带位于场氧化物区域之上。 熔丝结构还包括具有位于多晶硅条上的第一和第二区域的硅化金属化层。 第一区域具有第一厚度，并且第二区域具有小于第一厚度的第二厚度，并且基本上位于多晶硅条的增加的掺杂剂浓度区域之上。 优选地，硅化金属化层的第一区域具有位于第二区域的相对侧上的第一侧和第二侧，并且所得到的熔丝结构的形状基本上是矩形。 因此，可以通过断开第二区域来编程半导体熔丝结构。

公开(公告)号：US5854510A

公开(公告)日：1998-12-29

申请号：US883403

申请日：1997-06-26

申请人： Harlan Lee Sur, Jr. ,  Subhas Bothra ,  Xi-Wei Lin ,  Martin H. Manley ,  Robert Payne

发明人： Harlan Lee Sur, Jr. ,  Subhas Bothra ,  Xi-Wei Lin ,  Martin H. Manley ,  Robert Payne

IPC分类号： H01C13/00 ,  H01L21/822 ,  H01L23/525 ,  H01L27/04 ,  H01L27/10 ,  H01L29/00

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/3011

摘要： Disclosed is a semiconductor fuse structure having a low power programming threshold and anti-reverse engineering characteristics. The fuse structure includes a substrate having a field oxide region. A polysilicon strip that has an increased dopant concentration region lies over the field oxide region. The fuse structure further includes a silicided metallization layer having first and second regions lying over the polysilicon strip. The first region has a first thickness, and the second region has a second thickness that is less than the first thickness and is positioned substantially over the increased dopant concentration region of the polysilicon strip. Preferably, the first region of the silicided metallization layer has a first side and a second side located on opposite sides of the second region, and the resulting fuse structure is substantially rectangular in shape. Therefore, the semiconductor fuse structure can be programmed by breaking the second region.

摘要翻译： 公开了具有低功率编程阈值和抗逆向工程特性的半导体熔丝结构。 熔丝结构包括具有场氧化物区域的衬底。 具有增加的掺杂剂浓度区域的多晶硅条带位于场氧化物区域之上。 熔丝结构还包括具有位于多晶硅条上的第一和第二区域的硅化金属化层。 第一区域具有第一厚度，并且第二区域具有小于第一厚度的第二厚度，并且基本上位于多晶硅条的增加的掺杂剂浓度区域之上。 优选地，硅化金属化层的第一区域具有位于第二区域的相对侧上的第一侧和第二侧，并且所得到的熔丝结构的形状基本上是矩形。 因此，可以通过断开第二区域来编程半导体熔丝结构。

公开(公告)号：US5963784A

公开(公告)日：1999-10-05

申请号：US853853

申请日：1997-05-09

申请人： Subhas Bothra ,  Xi-Wei Lin

发明人： Subhas Bothra ,  Xi-Wei Lin

IPC分类号： H01L21/66 ,  H01L23/544 ,  G01R31/26 ,  G01R27/08

CPC分类号： H01L22/34 ,  H01L22/12

摘要： The present invention provides methods of determining a smallest dimension of a fabricated device on a semiconductor substrate, methods of determining width of a structure comprising a refractory metal silicide, methods of determining parameters of a semiconductor device comprising a refractory metal silicide, and methods of determining width of an insulative spacer of a semiconductor device. One aspect of the present invention provides a method of determining a smallest dimension of a fabricated device on a semiconductor substrate comprising: providing a first substrate area and a second substrate area; subjecting the first substrate area and the second substrate area to the same processing conditions to achieve regions of like material on the first and second substrate areas, the like material in the first area having a smallest dimension which is greater than a smallest dimension of the like material in the second area; determining parameters of the first substrate area; and determining said smallest dimension of the like material in the second substrate area using the determined parameters of the first substrate area.

摘要翻译： 本发明提供了确定半导体衬底上制造的器件的最小尺寸的方法，确定包括难熔金属硅化物的结构的宽度的方法，确定包括难熔金属硅化物的半导体器件的参数的方法，以及确定方法 半导体器件的绝缘间隔物的宽度。 本发明的一个方面提供一种确定半导体衬底上的制造器件的最小尺寸的方法，包括：提供第一衬底区域和第二衬底区域; 对第一基板区域和第二基板区域进行相同的处理条件以在第一和第二基板区域上实现类似材料的区域，第一区域中的类似材料具有大于等于最小尺寸的最小尺寸 第二区的材料; 确定第一衬底区域的参数; 以及使用所确定的所述第一衬底区域的参数来确定所述第二衬底区域中的所述相似材料的所述最小尺寸。

公开(公告)号：US5985749A

公开(公告)日：1999-11-16

申请号：US881614

申请日：1997-06-25

申请人： Xi-Wei Lin ,  Subhas Bothra

发明人： Xi-Wei Lin ,  Subhas Bothra

IPC分类号： H01L21/768 ,  H01L21/28

CPC分类号： H01L21/76843

摘要： The invention relates to integrated circuits and to via hole structures which include a tungsten silicide barrier layer and to methods of forming such via hole structures. In an exemplary embodiment, a metal layer is formed on a sidewall and a bottom surface of the via hole, a WSi.sub.x barrier layer is formed on the first metal layer by chemical vapor deposition and the via hole is subsequently filled with a metal. The tungsten silicide barrier layer effectively suppresses device degradation resulting from the release of gaseous species from the sidewall of the via hole during plug formation. Semiconductor devices can thus be fabricated which are immune or less susceptible to metal open failures due to incomplete via filling.

摘要翻译： 本发明涉及集成电路和包括硅化钨阻挡层的通孔结构以及形成这种通孔结构的方法。 在一个示例性实施例中，在通孔的侧壁和底表面上形成金属层，通过化学气相沉积在第一金属层上形成WSix阻挡层，随后填充金属孔。 硅化钨阻挡层有效地抑制了在插塞形成期间从气孔物质从通孔的侧壁释放出来的装置劣化。 因此可以制造半导体器件，其由于不完全的通孔填充而免疫或不易受金属开路故障的影响。

公开(公告)号：US5834356A

公开(公告)日：1998-11-10

申请号：US883814

申请日：1997-06-27

申请人： Subhas Bothra ,  Dipankar Pramanik ,  Xi-Wei Lin

发明人： Subhas Bothra ,  Dipankar Pramanik ,  Xi-Wei Lin

IPC分类号： H01L21/02 ,  H01L21/285 ,  H01L21/20

CPC分类号： H01L28/24 ,  H01L21/28518 ,  H01L28/20

摘要： Disclosed is a method for making a high resistive structure in a salicided process. The method includes providing a substrate including at least one active device having diffusion regions and a polysilicon gate structure. Depositing a metallization layer over the substrate including at least one active device. Annealing the substrate to cause at least part of metallization layer to form a metallization silicided layer over the substrate that includes the at least one active device. Preferably, the metallization silicided layer lying over the diffusion regions and the polysilicon gate produces a substantially decreased level of sheet resistance. The method also includes forming a mask over the metallization silicided layer, and the mask being configured to leave a portion of the metallization silicided layer that overlies at least one active device exposed. Further, the method includes etching the substrate in order to remove the exposed metallization silicided layer overlying the at least one active device to produce a substantially increased level of sheet resistance over the at least one active device not having the metallization silicided layer.

摘要翻译： 本发明公开了一种在水银工艺中制作高电阻结构的方法。 该方法包括提供包括至少一个具有扩散区的有源器件和多晶硅栅极结构的衬底。 在包括至少一个有源器件的衬底上沉积金属化层。 退火衬底以使至少部分金属化层在包括至少一个有源器件的衬底上形成金属化硅化物层。 优选地，位于扩散区域和多晶硅栅极上方的金属化硅化物层产生显着降低的薄层电阻水平。 该方法还包括在金属化硅化物层上形成掩模，并且掩模被配置为留下覆盖至少一个暴露的有源器件的金属化硅化物层的一部分。 此外，该方法包括蚀刻衬底以去除覆盖至少一个有源器件的暴露的金属化硅化物层，以在不具有金属化硅化物层的至少一个有源器件上产生基本上增加的片电阻水平。

公开(公告)号：US08701054B2

公开(公告)日：2014-04-15

申请号：US13237818

申请日：2011-09-20

申请人： Victor Moroz ,  Munkang Choi ,  Xi-Wei Lin

发明人： Victor Moroz ,  Munkang Choi ,  Xi-Wei Lin

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  H01L21/266 ,  H01L27/0207 ,  H01L29/1033 ,  H01L29/41758

摘要： Roughly described, the invention includes layouts and masks for an integrated circuit, in which the diffusion shape for a transistor includes a transversely extending jog on one or both transversely opposite sides, the jog having inner and outer corners, at least one of which is located relative to the gate conductor longitudinally such that during lithographic printing of the diffusion shape onto the integrated circuit, the corner will round and extend at least partly into the channel region. The invention also includes aspects for a system and method for introducing such jogs, and for an integrated circuit device having a non-rectangular channel region, the channel region being wider where it meets the source region than at some other longitudinal position under the gate.

摘要翻译： 粗略地描述，本发明包括用于集成电路的布局和掩模，其中晶体管的扩散形状包括在一个或两个横向相对侧上的横向延伸的点动，该点动具有内角和外角，其中至少一个位于 相对于栅极导体纵向，使得在将扩散形状平版印刷到集成电路上时，角部将圆形并且至少部分地延伸到沟道区域中。 本发明还包括用于引入这种点动的系统和方法以及用于具有非矩形通道区域的集成电路器件的方面，其中沟道区域在与栅极区域相比较宽的位置处比栅极下方的其它纵向位置更宽。

公开(公告)号：US20110309453A1

公开(公告)日：2011-12-22

申请号：US13221747

申请日：2011-08-30

申请人： Victor Moroz ,  Dipankar Pramanik ,  Xi-Wei Lin

发明人： Victor Moroz ,  Dipankar Pramanik ,  Xi-Wei Lin

IPC分类号： H01L27/092

CPC分类号： H01L21/823807 ,  H01L21/823878 ,  H01L29/7846

摘要： Roughly described, transistor channel regions are elevated over the level of certain adjacent STI regions. Preferably the STI regions that are transversely adjacent to the diffusion regions are suppressed, as are STI regions that are longitudinally adjacent to N-channel diffusion regions. Preferably STI regions that are longitudinally adjacent to P-channel diffusions are not suppressed; preferably they have an elevation that is at least as high as that of the diffusion regions.

摘要翻译： 粗略描述，晶体管沟道区域在某些相邻STI区域的水平上升高。 优选地，与扩散区横向相邻的STI区域被抑制，与N沟道扩散区域纵向相邻的STI区也是如此。 优选地，与P沟道扩散纵向相邻的STI区域不被抑制; 优选地，它们具有至少与扩散区域相同的高度。

公开(公告)号：US07681164B2

公开(公告)日：2010-03-16

申请号：US11848524

申请日：2007-08-31

申请人： Xi-Wei Lin ,  Victor Moroz

发明人： Xi-Wei Lin ,  Victor Moroz

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A system that places an integrated circuit (IC) device within an IC chip layout is presented. During operation, the system receives the IC device to be placed within the IC chip layout, wherein the IC chip layout includes one or more continuous rows of diffusion. Next, the system places the IC device within a continuous row of diffusion. The system then determines whether the IC device is to be electrically isolated from other IC devices. If so, the system inserts one or more isolation devices within the continuous row of diffusion so that the IC device can be electrically isolated from other IC devices. The system then biases the one or more isolation device so that the IC device is electrically isolated from other IC devices within the continuous row of diffusion.

摘要翻译： 提出了一种将集成电路（IC）器件放置在IC芯片布局内的系统。 在操作期间，系统接收要放置在IC芯片布局内的IC器件，其中IC芯片布局包括一个或多个连续的扩散行。 接下来，系统将IC器件放置在连续的扩散行内。 然后，系统确定IC器件是否与其他IC器件电隔离。 如果是这样，系统将一个或多个隔离装置插入连续的扩散行内，使得IC器件可以与其它IC器件电隔离。 然后，该系统偏置一个或多个隔离装置，使得IC器件与连续的扩散排中的其它IC器件电隔离。

公开(公告)号：US20090319960A1

公开(公告)日：2009-12-24

申请号：US12505357

申请日：2009-07-17

申请人： Xi-Wei Lin

发明人： Xi-Wei Lin

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5068 ,  G06F2217/10

摘要： Roughly described, method and apparatus for laying out an integrated circuit, in which a subject interconnect has predetermined values for a plurality of variables affecting propagation delay of the subject interconnect. The value of an adjustment one of the variables is adjusted to minimize exposure of the propagation delay of the interconnect to process variations causing variations in the value of a subject fabrication variable, and a revised layout is developed in dependence upon the adjusted value for the adjustment variable. In an embodiment, the adjustment is made in dependence upon a pre-calculated “interconnect optimization database” indicating combinations of values for the plurality of variables which have been pre-determined to minimize exposure of interconnect propagation delay to process variations affecting the subject variable. Different databases, or different entries in the same database, can be provided for minimizing exposure of interconnect propagation delay to process variations affecting each subject variable of interest.

摘要翻译： 粗略地描述了用于布置集成电路的方法和装置，其中对象互连对于影响对象互连的传播延迟的多个变量具有预定值。 调整一个变量的值被调整以最小化互连的传播延迟的暴露，从而导致主题制造变量的值的变化导致处理变化的变化，并且根据调节的调整值来开发修改的布局 变量。 在一个实施例中，根据预先计算的“互连优化数据库”进行调整，所述“互连优化数据库”指示已经预先确定的多个变量的值的组合，以使互连传播延迟的曝光最小化以影响影响主题变量的处理变化。 可以提供不同的数据库或相同数据库中的不同条目，用于最小化互连传播延迟对影响感兴趣的每个受试者变量的处理变化的暴露。

公开(公告)号：US07542891B2

公开(公告)日：2009-06-02

申请号：US11470978

申请日：2006-09-07

申请人： Xi-Wei Lin ,  Victor Moroz ,  Dipankar Pramanik

发明人： Xi-Wei Lin ,  Victor Moroz ,  Dipankar Pramanik

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： Roughly described, standard SPICE models can be modified by substituting a different stress analyzer to better model the stress adjusted characteristics of a transistor. A first, standard, stress-sensitive, transistor model is used to develop a mathematical relationship between the first transistor performance measure and one or more instance parameters that are available as inputs to a second, stress-insensitive, transistor model. The second transistor model may for example be the same as the first model, with its stress sensitivity disabled. Thereafter, a substitute stress analyzer can be used to determine a stress-adjusted value for the first performance measure, and the mathematical relationship can be used to convert that value into specific values for the one or more instance parameters. These values are then provided to the second transistor model for use in simulating the characteristics of the particular transistor during circuit simulation.

摘要翻译： 粗略描述，可以通过替代不同的应力分析器来更好地模拟晶体管的应力调整特性来修改标准SPICE模型。 第一，标准，应力敏感的晶体管模型用于开发第一晶体管性能测量与可用作第二，不应力敏感晶体管模型的输入的一个或多个实例参数之间的数学关系。 第二晶体管模型可以例如与第一模型相同，其应力灵敏度被禁用。 此后，可以使用替代应力分析器来确定用于第一性能测量的应力调整值，并且可以使用数学关系将该值转换为一个或多个实例参数的特定值。 然后将这些值提供给第二晶体管模型，以用于在电路仿真期间模拟特定晶体管的特性。