公开(公告)号：US06581141B1

公开(公告)日：2003-06-17

申请号：US09314045

申请日：1999-05-18

申请人： Richard Allen Kelley ,  Danny Marvin Neal ,  Adalberto Guillermo Yanes

发明人： Richard Allen Kelley ,  Danny Marvin Neal ,  Adalberto Guillermo Yanes

IPC分类号： G06F1316

CPC分类号： G06F13/4059

摘要： A system and method for optimally processing split request transactions across a PCI-X bridge with a PCI-X bridge buffer. The split transaction mode of the PCI-X bridge buffer is toggled between a No Over-commit mode and an over-commit mode. Over-commitment of the buffer is inhibited when the split transaction mode is toggled to the No Over-commit mode and when the buffer is over committed by the bridge. At least some over-commitment of the buffer is allowed by the bridge when the split transaction mode is toggled to the over-commit mode and when the buffer is not over committed by the bridge. The over-commit mode may be an Over-commitment mode or a Flood mode. The Over-commitment mode allows some degree of over commitment of the buffer by the bridge while the Flood mode allows the bridge to forward all split request transactions regardless of size of the transactions or amount of available space in the buffer when the Over-commit mode is in a Flood mode. The split request transaction is controlled and forwarded based on the toggled split transaction mode. The system comprises at least a toggle switch and a control system. The split transaction mode is toggled to or maintained at a particular mode based on whether a retry or disconnect of the split completion transaction by the PCI-X bridge has or has not occurred and whether the buffer is or is not over committed.

摘要翻译： 一种用于通过PCI-X桥接缓冲区优化处理跨PCI-X网桥的分离请求事务的系统和方法。 PCI-X桥接缓冲区的拆分事务模式在无提交模式和过度提交模式之间切换。 当分割事务模式切换到“否”超过提交模式时，以及缓冲区由桥接器过渡时，缓冲区的过度承诺将被禁止。 当分裂事务模式切换到过度提交模式时，并且缓冲区未超过桥接器时，桥接器允许缓冲区的至少一些过度承诺。 过度提交模式可能是过度承诺模式或洪水模式。 过度承诺模式允许桥接器缓冲区过度承担一定程度，而洪泛模式允许桥接器转发所有拆分请求事务，而不管事务的大小或缓冲区中的可用空间量，当过度提交模式 处于泛洪模式。 分割请求事务基于切换的分组事务模式进行控制和转发。 该系统至少包括拨动开关和控制系统。 基于PCI-X网桥的分裂完成事务的重试或断开是否已经发生或者没有发生以及缓冲器是否还未被提交，分割事务模式被切换到或维持在特定模式。

公开(公告)号：US06519555B1

公开(公告)日：2003-02-11

申请号：US08723174

申请日：1996-09-30

申请人： Richard Allen Kelley ,  Danny Marvin Neal ,  Michael Anthony Perez ,  Paul Gordon Robertson ,  Padmavathy Tamirisa ,  John Daniel Upton

发明人： Richard Allen Kelley ,  Danny Marvin Neal ,  Michael Anthony Perez ,  Paul Gordon Robertson ,  Padmavathy Tamirisa ,  John Daniel Upton

IPC分类号： G06F1750

CPC分类号： G06F13/4045

摘要： The invention provides an apparatus and method of allowing a device to respond to a configuration query only if it is the true target of the query. In one embodiment of the invention, logic gates having two inputs are provided. The first input of the logic gates is connected to the signal of a bridge that selects a device when the address of the signal is referenced in the configuration query. The second input of the logic gate receives a signal indicating whether the local bus or the subordinate bus is being configured and the output of the logic gate is used to enable the device. In a second embodiment, certain signals designated to indicate the selection of a bus are used to enable devices to respond to configuration queries.

摘要翻译： 本发明提供一种允许设备仅在查询的真实目标时才响应配置查询的装置和方法。 在本发明的一个实施例中，提供了具有两个输入的逻辑门。 当在配置查询中引用信号的地址时，逻辑门的第一输入连接到选择设备的桥的信号。 逻辑门的第二输入接收指示本地总线或下级总线是否被配置的信号，并且使用逻辑门的输出来使能该器件。 在第二实施例中，指定用于指示总线选择的某些信号用于使得设备能够响应配置查询。

公开(公告)号：US06483720B1

公开(公告)日：2002-11-19

申请号：US09640512

申请日：2000-08-17

申请人： Patrick H. Buffet ,  Paul Lee Clouser ,  Danny Marvin Neal

发明人： Patrick H. Buffet ,  Paul Lee Clouser ,  Danny Marvin Neal

IPC分类号： H05K900

CPC分类号： H05K1/0218 ,  G06F1/182 ,  G06F1/183 ,  G06F1/189

摘要： A method and implementing electronic tri-plate connection system are provided including a nested set of RF Faraday cages within the system with integrated circuit packages containing the core drivers and receivers as the innermost Faraday cage, and additional Faraday cages being implemented at each outward level through card, board, backplane and unit level and into the network level. There is no distinction between power ground, signal ground or shield ground. All grounds throughout the system are at the same level and all package ground levels are interconnected.

摘要翻译： 提供了一种方法和实现电子三板连接系统，包括系统内的嵌套式RF法拉第笼式集成电路，其集成电路封装包含核心驱动器和接收器作为最内层的法拉第笼，另外的法拉第笼在每个向外的水平 卡，板，背板和单元级别，并进入网络级。 电源地，信号地或屏蔽地之间没有区别。 整个系统中的所有场地处于同一水平，所有包装地面水平相互连接。

公开(公告)号：US06477057B1

公开(公告)日：2002-11-05

申请号：US09640538

申请日：2000-08-17

申请人： Patrick H. Buffet ,  Paul Lee Clouser ,  Danny Marvin Neal

发明人： Patrick H. Buffet ,  Paul Lee Clouser ,  Danny Marvin Neal

IPC分类号： H05K702

CPC分类号： H05K1/0216 ,  G06F1/189 ,  G06F1/26 ,  H05K1/0231 ,  H05K2201/09345 ,  H05K2201/09663

摘要： A method and implementing computer system are provided in which de-coupling capacitors are used at driver and receiver sources, and defined gaps are created separating power and ground areas on a voltage reference plane of a circuit board. Short-circuit via connections are also provided through one or more vias between spatially separated circuit board layers. Each driver or receiver module includes the driver or receiver along with an associated gap, capacitor and via connections to VDD and ground planes, all included within a defined proximity to effectively block switching energy and/or VDD noise from entering the tri-plate ground-to-ground reference system. In a related exemplary construction, signal lines are placed at predetermined positions between ground planes to provide a tri-plate circuit board structure for transmitting logic signals from a driver to one or more receivers.

摘要翻译： 提供了一种方法和实现的计算机系统，其中在驱动器和接收器源处使用解耦电容器，并且在电路板的电压参考平面上分离电源和接地区域来创建限定的间隙。 通过连接的短路也通过空间分离的电路板层之间的一个或多个通孔提供。 每个驱动器或接收器模块包括驱动器或接收器以及相关联的间隙，电容器和到VDD和接地层的通孔连接，所有这些都包括在限定的接近度内，以有效地阻止开关能量和/或VDD噪声进入三板接地平面， 对地参考系统。 在相关的示例性结构中，信号线被放置在接地平面之间的预定位置处，以提供用于将逻辑信号从驾驶员发送到一个或多个接收器的三板电路板结构。

公开(公告)号：US06405276B1

公开(公告)日：2002-06-11

申请号：US09210135

申请日：1998-12-10

申请人： Wen-Tzer Thomas Chen ,  Richard A. Kelley ,  Danny Marvin Neal ,  Steven Mark Thurber

发明人： Wen-Tzer Thomas Chen ,  Richard A. Kelley ,  Danny Marvin Neal ,  Steven Mark Thurber

IPC分类号： G06F1338

CPC分类号： G06F13/4059 ,  G06F13/4031

摘要： A bus bridge with a pool of buffers sets including first and second buffer sets. The bridge includes steering logic for directing transactions issued by a first peripheral device to the first buffer set and transactions issued by the second peripheral device to the second buffer set. The bus bridge is configured to pull posted memory write transactions ahead of a delayed read completion transaction in the first buffer set in response to identifying the first peripheral device as a target of a read request issued by a processor. In one embodiment, the bus bridge is further configured to receive first and second device select signals from the first and second peripheral devices respectively. In this embodiment, the device select signals indicate the target of the read request issued by the processor. The bridge is configured, in one embodiment, such that the pulling of posted memory write transactions in the first buffer set leaves transactions in all buffer sets other than the first buffer set unaffected in response to the read request. The invention further contemplates a computer system that includes a processor coupled to a system memory via a host bus and a bus bridge as described coupled between the host bus and a secondary bus. The bridge is most preferably configured such that transactions issued by the first peripheral device are stored in the first buffer set and transactions issued by the second peripheral device are stored in the second buffer set. In one embodiment, the device driver is designed to issue the load request in response to receiving an interrupt or to check status in the device. The source of the interrupt is preferably the target of the load request.

摘要翻译： 具有缓冲器集合的总线桥，包括第一和第二缓冲器组。 该桥包括用于将由第一外围设备发出的交易指向第一缓冲器组的转向逻辑，以及由第二外围设备向第二缓冲器组发出的事务。 总线桥被配置为响应于将第一外围设备识别为由处理器发出的读取请求的目标，在第一缓冲器集合中的延迟读取完成事务之前拉动已存储的写入事务。 在一个实施例中，总线桥还被配置为分别从第一和第二外围设备接收第一和第二设备选择信号。 在本实施例中，设备选择信号指示由处理器发出的读取请求的目标。 在一个实施例中，桥被配置为使得在第一缓冲器组中拉动已发布的存储器写入事务使得除了响应于读取请求不受影响的第一缓冲器集之外的所有缓冲器集中的事务。 本发明进一步设想一种计算机系统，其包括经由主机总线和总线桥连接到系统存储器的处理器，其耦合在主机总线和辅助总线之间。 该桥最优选地配置为使得由第一外围设备发出的交易存储在第一缓冲器组中，并且由第二外围设备发出的事务存储在第二缓冲器组中。 在一个实施例中，设备驱动器被设计为响应于接收到中断或检查设备中的状态而发出加载请求。 中断源最好是加载请求的目标。

公开(公告)号：US06295568B1

公开(公告)日：2001-09-25

申请号：US09055414

申请日：1998-04-06

申请人： Richard Allen Kelley ,  Danny Marvin Neal ,  Steven Mark Thurber

发明人： Richard Allen Kelley ,  Danny Marvin Neal ,  Steven Mark Thurber

IPC分类号： G06F1338

CPC分类号： G06F13/4022

摘要： A method and system for supporting multiple Peripheral Component Interconnect (PCI) local buses through a single PCI host bridge having multiple PCI interfaces within a data-processing system are disclosed. In accordance with the method and system of the present invention, a processor and a system memory are connected to a system bus. One or more PCI local buses are connected to the system bus through a single PCI host bridge having bus and frequency control logic and bus clocks. The PCI local buses include sets of in-line electronic switches, dividing each PCI local bus into PCI local bus segments for supporting more PCI peripheral component slots then are called out by the PCI local bus standard. The sets of in-line electronic switches are open and closed in accordance with the bus and frequency control logic within the PCI host bridge thereby allowing the PCI peripheral component slots to operate at different bus frequencies, including bus frequencies higher than 66 MHz by using the bus clocks. The sets of in-line electronic switches further allowing different bus segments on the same PCI logical bus to dynamically be operated at different frequencies.

摘要翻译： 公开了一种通过在数据处理系统内具有多个PCI接口的单个​​PCI主机桥来支持多个外围组件互连（PCI）局部总线的方法和系统。 根据本发明的方法和系统，处理器和系统存储器连接到系统总线。 一个或多个PCI本地总线通过具有总线和频率控制逻辑和总线时钟的单个PCI主机桥连接到系统总线。 PCI本地总线包括一系列在线电子开关，将每个PCI本地总线划分为PCI本地总线段，以支持更多的PCI外设组件插槽，然后由PCI本地总线标准进行调用。 这些串联式电子开关根据PCI主机桥内的总线和频率控制逻辑开启和关闭，从而允许PCI外设组件插槽在不同的总线频率下工作，包括高于66MHz的总线频率，通过使用 总线时钟 这些在线电子开关进一步允许在同一PCI逻辑总线上的不同总线段动态地以不同的频率工作。

公开(公告)号：US06229334B1

公开(公告)日：2001-05-08

申请号：US09163916

申请日：1998-09-30

申请人： Richard Allen Kelley ,  Danny Marvin Neal

发明人： Richard Allen Kelley ,  Danny Marvin Neal

IPC分类号： H03K1716

CPC分类号： G06F13/4072

摘要： A method and implementing computer system is provided in which PCI bus load conditions are detected and dummy loads are selectively switched into the PCI bus under light load conditions in order to avoid voltage overshoot problems. Load control logic receives input signals representative of the presence or absence of adapters connected into PCI slots. The load control logic is connected to load control switches. The load control switches are arranged to selectively connect to the PCI slot or to a dummy load. The load control system is selectively operable, by controlling the load switches, to connect dummy loads into empty PCI slots to dampen the bus when light load conditions are detected to exist on the PCI bus. In a PCI system hot plug environment, the system is operable to quiesce the slot being hot plugged so that the adapter can be removed or inserted into a PCI slot while maintaining acceptable PCI bus loading conditions.

摘要翻译： 提供了一种方法和实现的计算机系统，其中检测到PCI总线负载条件，并且在轻负载条件下将虚拟负载选择性地切换到PCI总线，以避免电压过冲问题。 负载控制逻辑接收代表连接到PCI插槽中的适配器的存在或不存在的输入信号。 负载控制逻辑连接到负载控制开关。 负载控制开关被布置成选择性地连接到PCI插槽或虚拟负载。 通过控制负载开关，负载控制系统通过控制负载开关将虚拟负载连接到空的PCI插槽中，以便在PCI总线上检测到轻负载条件时抑制总线。 在PCI系统热插拔环境中，该系统可操作以停止正在热插拔的插槽，以便可以将适配器移除或插入PCI插槽，同时保持可接受的PCI总线负载条件。

公开(公告)号：US06223299B1

公开(公告)日：2001-04-24

申请号：US09072418

申请日：1998-05-04

申请人： Douglas Craig Bossen ,  Charles Andrew McLaughlin ,  Danny Marvin Neal ,  James Otto Nicholson ,  Steven Mark Thurber

发明人： Douglas Craig Bossen ,  Charles Andrew McLaughlin ,  Danny Marvin Neal ,  James Otto Nicholson ,  Steven Mark Thurber

IPC分类号： G06F1100

CPC分类号： G06F11/0772 ,  G06F11/0745 ,  G06F11/0793

摘要： Device selects lines from each I/O device are brought into a PCI host bridge individually so that the device number of a failing device may be logged in an error register when an error is seen on the PCI bus. Until the error register is reset, subsequent load and store operations are delayed until the device number of the subject device may be checked against the error register. If the subject device is a previously failing device, the load/store operation to that device is prevented from completing, either by forcing bad parity or zeroing all byte enables. By forcing bad parity of zero byte enables, the I/O device will respond to the load or store request by activating its device select line, but will not accept store data. Operations to devices which are not logged in the error register are permitted to proceed normally, as are all load store operations when the error register is clear. Normal system operations are thus not impacted, and operations during error recovery are permitted to proceed if no further damage will be caused by such operations.

摘要翻译： 设备选择每个I / O设备的线路分别插入PCI主机桥，以便在PCI总线上出现错误时，可能会将故障设备的设备号记录在错误寄存器中。 在错误寄存器复位之前，后续的加载和存储操作将被延迟，直到可以针对错误寄存器检查主体设备的设备编号。 如果主机设备是先前发生故障的设备，则通过强制坏的奇偶校验或归零所有字节使能来防止对该设备的加载/存储操作完成。 通过强制零字节的不良奇偶使能，I / O设备将通过激活其设备选择行来响应加载或存储请求，但不接受存储数据。 允许对未登录在错误寄存器中的设备进行操作，正常情况下，正常情况下进行加载存储操作。 因此，正常的系统操作不会受到影响，并且如果这种操作不会造成进一步的损坏，则允许错误恢复期间的操作进行。

公开(公告)号：US06189789B1

公开(公告)日：2001-02-20

申请号：US09149709

申请日：1998-09-09

申请人： Frank Eliot Levine ,  Danny Marvin Neal

发明人： Frank Eliot Levine ,  Danny Marvin Neal

IPC分类号： G06K1500

CPC分类号： G07F7/02 ,  G06Q20/208 ,  G06Q20/343 ,  G07G1/0054 ,  G07G1/0072

摘要： A method and system for a merchandise checkout system utilizes a remote scanning device, a shopping cart and bags for allowing a purchaser to buy merchandise unassisted by store personnel. The remote scanning device reads product identity information from coded levels on products chosen by the purchaser and sends the information to a central processor. The central processor has a memory, which indexes price information and weight for each product based on the product identity information. The central processor sends an accumulated price and weight transaction to the remote scanning device for the purchaser's use. The product identity information on the products further include a security tag device which is deactivated by the remote scanning device. The purchaser upon completion of their purchases takes their shopping cart to a security station for weighing in on a scale wherein an actual combined weight of the shopping cart, bags and products is compared to a predicted weight determined by the central processor and generating a notification signal if a discrepancy occurs. The security station further verifies that the security tag devices have been deactivated and also generates a notification signal. The purchaser next goes to a payment checkout terminal coupled to the central processor, wherein the payment checkout terminal effects financial transactions including acceptance of payment for transactions initiated by the remote scanning device, and the payment checkout terminal is operable by store personnel only.

摘要翻译： 用于商品结帐系统的方法和系统利用远程扫描装置，购物车和袋子，用于允许购买者购买商店人员协助的商品。 远程扫描设备从购买者选择的产品的编码级别读取产品标识信息，并将信息发送到中央处理器。 中央处理器具有存储器，其基于产品身份信息来索引每个产品的价格信息和权重。 中央处理器向远程扫描设备发送累积的价格和重量交易以供购买者使用。 关于产品的产品身份信息还包括由远程扫描设备停用的安全标签设备。 购买者在购买完成后将其购物车带到安全站，以秤量进行称重，其中将购物车，行李箱和产品的实际组合重量与由中央处理器确定的预测重量进行比较，并产生通知信号 如果出现差异 安全站进一步验证安全标签设备已被停用，并且还产生通知信号。 接下来，购买者去耦合到中央处理器的支付结账终端，其中支付结账终端影响金融交易，包括接受由远程扫描装置发起的交易的支付，支付结账终端仅由商店人员操作。

公开(公告)号：US6081861A

公开(公告)日：2000-06-27

申请号：US94712

申请日：1998-06-15

申请人： Richard Allen Kelley ,  Danny Marvin Neal

发明人： Richard Allen Kelley ,  Danny Marvin Neal

IPC分类号： G06F13/24 ,  G06F13/40 ,  G06F13/38

CPC分类号： G06F13/4027 ,  G06F13/24

摘要： A method and implementing system are provided which includes a PCI host bridge connected to a PCI bus. The PCI slots are applied to a switch array which is controlled by circuitry within the PCI host bridge in the example. The switch array is connected to interrupt control logic which is, in turn, coupled to the PCI host bridge. The methodology in one example uses the Interrupt Pin field in the PCI configuration space currently supported by the PCI Specification to identify an ISA interrupt signal line to which a migrated ISA device needs to be connected. Migrated ISA devices in PCI card connectors are then identified by determining the interrupt information associated with the ISA interrupt signal line identification method used. An interrupt switch array is then used to connect the migrated ISA device interrupt to the desired IRQx signal line and to the interrupt control logic. The switching array provides for a translation of PCI to ISA interrupts for connection to an interrupt controller.

摘要翻译： 提供了一种方法和实现系统，其包括连接到PCI总线的PCI主机桥。 PCI插槽被应用于在示例中由PCI主机桥内的电路控制的开关阵列。 开关阵列连接到中断控制逻辑，中断控制逻辑又连接到PCI主机桥。 一个示例中的方法使用PCI规范目前支持的PCI配置空间中的中断引脚字段来标识需要连接迁移的ISA设备的ISA中断信号线。 然后通过确定与所使用的ISA中断信号线识别方法相关联的中断信息来识别PCI卡连接器中的ISA设备。 然后使用中断开关阵列将迁移的ISA设备中断连接到所需的IRQx信号线和中断控制逻辑。 开关阵列提供PCI到ISA中断的转换，以连接到中断控制器。