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    Oxide semiconductor device
    74.
    发明授权
    Oxide semiconductor device 有权

    公开(公告)号：US09059298B2

    公开(公告)日：2015-06-16

    申请号：US14472618

    申请日：2014-08-29

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shunpei Yamazaki ,  Hiroki Ohara ,  Toshinari Sasaki ,  Kosei Noda ,  Hideaki Kuwabara

    IPC: H01L29/786 ,  H01L27/12 ,  H01L29/51

    Abstract: An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.

    Semiconductor device
    75.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09024313B2

    公开(公告)日：2015-05-05

    申请号：US13860812

    申请日：2013-04-11

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shunpei Yamazaki ,  Junichiro Sakata ,  Hiroki Ohara ,  Hideaki Kuwabara

    IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66

    CPC classification number: H01L27/3262 ,  G06F1/163 ,  H01L21/02614 ,  H01L27/1218 ,  H01L27/1222 ,  H01L27/1225 ,  H01L29/04 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/7869 ,  H01L29/78696 ,  H04B1/16

    Abstract: One object is to provide a semiconductor device with a structure which enables reduction in parasitic capacitance sufficiently between wirings. In a bottom-gate type thin film transistor including a stacked layer of a first layer which is a metal thin film oxidized partly or entirely and an oxide semiconductor layer, the following oxide insulating layers are formed together: an oxide insulating layer serving as a channel protective layer which is over and in contact with a part of the oxide semiconductor layer overlapping with a gate electrode layer; and an oxide insulating layer which covers a peripheral portion and a side surface of the stacked oxide semiconductor layer.

    Abstract translation: 一个目的是提供具有能够在布线之间充分降低寄生电容的结构的半导体器件。 在包括作为部分或全部氧化的金属薄膜的第一层的堆叠层和氧化物半导体层的底栅型薄膜晶体管中，形成以下氧化物绝缘层：作为沟道的氧化物绝缘层 与氧化物半导体层的与栅电极层重叠的部分结合并接触的保护层; 以及覆盖层叠的氧化物半导体层的周边部分和侧面的氧化物绝缘层。

    METHOD FOR MANUFACTURING OXIDE SEMICONDUCTOR DEVICE
    76.
    发明申请
    METHOD FOR MANUFACTURING OXIDE SEMICONDUCTOR DEVICE 有权
    制造氧化物半导体器件的方法

    公开(公告)号：US20140367680A1

    公开(公告)日：2014-12-18

    申请号：US14472618

    申请日：2014-08-29

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shunpei Yamazaki ,  Hiroki Ohara ,  Toshinari Sasaki ,  Kosei Noda ,  Hideaki Kuwabara

    IPC: H01L29/786

    CPC classification number: H01L27/1225 ,  G02F1/133345 ,  G02F1/1337 ,  G02F1/134309 ,  G02F1/136227 ,  G02F1/136277 ,  G02F1/1368 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/24 ,  H01L29/517 ,  H01L29/78609 ,  H01L29/7869

    Abstract: An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.

    Abstract translation: 目的在于提供一种半导体器件，其具有可以充分降低布线之间的寄生电容的结构。 用作沟道保护层的氧化物绝缘层形成在与栅电极层重叠的氧化物半导体层的一部分上。 在与氧化物绝缘层的形成相同的步骤中，形成覆盖氧化物半导体层的周边部分的氧化物绝缘层。 设置覆盖氧化物半导体层的周边部分的氧化物绝缘层以增加栅极电极层与形成在栅电极层的上方或周围的布线层之间的距离，从而降低寄生电容。

    Method for manufacturing semiconductor device
    79.
    发明授权
    Method for manufacturing semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US08623698B2

    公开(公告)日：2014-01-07

    申请号：US13783672

    申请日：2013-03-04

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Toshinari Sasaki ,  Junichiro Sakata ,  Hiroki Ohara ,  Shunpei Yamazaki

    IPC: H01L21/16

    CPC classification number: H01L21/477 ,  H01L21/02565 ,  H01L21/02664 ,  H01L21/383 ,  H01L21/46 ,  H01L27/1225 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693

    Abstract: An object is to manufacture a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a method for manufacturing a semiconductor device including a thin film transistor in which an oxide semiconductor film is used for a semiconductor layer including a channel formation region, heat treatment (for dehydration or dehydrogenation) is performed to improve the purity of the oxide semiconductor film and reduce impurities including moisture or the like. After that, slow cooling is performed under an oxygen atmosphere. Besides impurities including moisture or the like exiting in the oxide semiconductor film, heat treatment causes reduction of impurities including moisture or the like exiting in a gate insulating layer and those in interfaces between the oxide semiconductor film and films which are provided over and below the oxide semiconductor and in contact therewith.

    Abstract translation: 本发明的目的是制造具有稳定电特性的薄膜晶体管的高度可靠的半导体器件。 在包括使用氧化物半导体膜用于包括沟道形成区域的半导体层的薄膜晶体管的半导体器件的制造方法中，进行热处理（脱水或脱氢）以提高氧化物半导体膜的纯度 并减少杂质，包括水分等。 之后，在氧气氛下进行缓慢冷却。 除了在氧化物半导体膜中排出的含有水分等的杂质以外，热处理会导致在栅极绝缘层中退出的杂质，包括氧化物半导体膜和膜之间的界面中的杂质，氧化物半导体膜和氧化物之间和之下的界面 半导体并与其接触。

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