公开(公告)号：US5999571A

公开(公告)日：1999-12-07

申请号：US539816

申请日：1995-10-05

申请人： Yeshik Shin ,  Kyeongho Lee ,  Sungjoon Kim ,  David Lee

发明人： Yeshik Shin ,  Kyeongho Lee ,  Sungjoon Kim ,  David Lee

IPC分类号： H03M7/14 ,  H04L7/00 ,  H04L7/04 ,  H04L25/03 ,  H04L25/08 ,  H04L25/49 ,  H04N7/083 ,  H04N7/52 ,  H04J3/06 ,  H04J3/17 ,  H04L7/06

CPC分类号： H04N7/52 ,  H04L25/03866 ,  H04L25/085 ,  H04L25/4915 ,  H04N21/4305 ,  H04N7/083 ,  H04L2007/045 ,  H04L7/0008 ,  H04N21/23602 ,  H04N21/4342

摘要： A method and apparatus for producing a transition-controlled, DC-balanced sequence of characters from an input sequence of data bytes is disclosed herein. The bits in each of the data bytes are selectively complemented in accordance with the number of logical transitions in each data byte in order to produce selectively complemented data blocks. A cumulative disparity is then determined between the logical values of different type included within ones of the selectively complemented data blocks previously encoded into characters. In addition, a current disparity in a candidate character associated with a current one of the selectively complemented data blocks being encoded is also determined. The candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of a polarity opposite to a first polarity of the cumulative disparity. Alternately, the complement of the candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of the first polarity. In a high-transition mode of operation, the bits within data blocks including less than a minimum number of logical transitions are selectively complemented so that each such selectively complemented data block includes in excess of the minimum number of logical transitions. In a low-transition mode of operation, the bits within data blocks having more than a predefined number of logical transitions are selectively complemented so that each such selectively complemented data block includes less than the maximum number of logical transitions.

摘要翻译： 本文公开了一种用于从数据字节的输入序列产生转换控制的直流平衡字符序列的方法和装置。 每个数据字节中的位根据每个数据字节中的逻辑转换的数量来选择性地补充，以便产生选择性补充的数据块。 然后在包括在先前编码为字符的选择性补充的数据块中的不同类型的逻辑值之前确定累积差异。 此外，还确定与被编码的选择性补充的数据块中的当前一个相关联的候选字符中的当前差异。 如果当前视差与累积视差的第一极性相反的极性，则候选字符被分配给选择性补充的数据块中的当前一个。 或者，如果当前视差是第一极性，则候选字符的补码被分配给选择性补充的数据块中的当前一个。 在高转换操作模式中，选择性地补充包括小于最小数量的逻辑转换的数据块内的位，使得每个这样的选择性补充的数据块包括超过最小数量的逻辑转换。 在低转换操作模式中，选择性地补充具有多于预定数量的逻辑转换的数据块内的位，使得每个这样的选择性补充的数据块包括小于逻辑转换的最大数量。

公开(公告)号：US5974464A

公开(公告)日：1999-10-26

申请号：US723694

申请日：1996-09-30

申请人： Yeshik Shin ,  Kyeongho Lee ,  Sungjoon Kim ,  David D. Lee

发明人： Yeshik Shin ,  Kyeongho Lee ,  Sungjoon Kim ,  David D. Lee

IPC分类号： H04N7/08 ,  G09G3/20 ,  G09G5/00 ,  H03M5/14 ,  H03M7/14 ,  H04L7/00 ,  H04L7/04 ,  H04L25/02 ,  H04L25/08 ,  H04L25/49 ,  H04N7/081 ,  H04N7/083 ,  H04N7/52 ,  H04N21/2368 ,  H04N21/434 ,  G06F13/38 ,  G06F15/17

CPC分类号： G09G5/006 ,  H04L25/085 ,  H04L25/4915 ,  H04N21/4305 ,  H04N7/083 ,  H04N7/52 ,  G09G2370/045 ,  G09G3/20 ,  G09G5/008 ,  H04L2007/045 ,  H04L7/0008 ,  H04L7/041 ,  H04N21/23602 ,  H04N21/4342

摘要： A new high-speed digital interface for transmitting video information over various transmission media including terminated copper wires such as twisted-pair wires and fiber optical cable is described. The significance of this new interface is that (1) it only uses a small number of data channels with all timing and control data embedded in data transmission, (2) it uses a transition controlled binary DC balanced coding for reliable, low-power and high-speed data transmission, (3) it uses low-swing differential voltage which minimizes EMI, and (4) it can be implemented in low-cost scaleable CMOS technology as a megacell or standard IC. The high-speed digital interface incorporates a method and apparatus for producing a transition-controlled, DC-balanced sequence of characters from an input sequence of data bytes. The bits in each of the data bytes are selectively complemented in accordance with the number of logical transitions in each data byte in order to produce selectively complemented data blocks. A cumulative disparity is then determined between the logical values of different type included within ones of the selectively complemented data blocks previously encoded into characters. In addition, a current disparity in a candidate character associated with a current one of the selectively complemented data blocks being encoded is also determined. The candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of a polarity opposite to a first polarity of the cumulative disparity. Alternately, the complement of the candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of the first polarity. In a high-transition mode of operation, the bits within data blocks including less than a minimum number of logical transitions are selectively complemented so that each such selectively complemented data block includes in excess of the minimum number of logical transitions. In a low-transition mode of operation, the bits within data blocks having more than a predefined number of logical transitions are selectively complemented so that each such selectively complemented data block includes less than the maximum number of logical transitions.

公开(公告)号：US5969552A

公开(公告)日：1999-10-19

申请号：US7707

申请日：1998-01-15

申请人： Kyeongho Lee ,  Yongsam Moon ,  Deog-Kyoon Jeong

发明人： Kyeongho Lee ,  Yongsam Moon ,  Deog-Kyoon Jeong

IPC分类号： G06F1/10 ,  G11C11/407 ,  H03L7/00 ,  H03L7/07 ,  H03L7/081 ,  H03L7/087 ,  H03L7/10 ,  H03L7/113 ,  H04L7/033 ,  H03K5/13

CPC分类号： H03L7/07 ,  H03L7/081 ,  H03L7/10 ,  H03L7/087

摘要： A device and method for synchronizing a local clock to a reference clock. The device uses a frequency acquisition loop and a phase acquisition loop. The frequency acquisition loop delays the reference clock to produce an intermediate clock which falls within the operating range of the phase acquisition loop. The phase acquisition loop then delays the intermediate clock to produce a local clock synchronized to the reference clock.

摘要翻译： 一种用于将本地时钟同步到参考时钟的装置和方法。 该器件使用频率采集回路和相位采集回路。 频率采集环路延迟参考时钟以产生落在相位采集环路的工作范围内的中间时钟。 相位采集环路延迟中间时钟以产生与参考时钟同步的本地时钟。

公开(公告)号：US20080026695A1

公开(公告)日：2008-01-31

申请号：US11878938

申请日：2007-07-27

申请人： Hyo Choi ,  Jin Jeon ,  Dae Kim ,  Kyeongho Lee ,  Sang Shim ,  Won Song

发明人： Hyo Choi ,  Jin Jeon ,  Dae Kim ,  Kyeongho Lee ,  Sang Shim ,  Won Song

IPC分类号： H04B7/00 ,  H04Q7/20

CPC分类号： H04W16/14 ,  H04W88/06 ,  H04W88/10

摘要： Embodiments of methods and systems of the application can transmit data (e.g., voice) using a wireless LAN and a Bluetooth. One system embodiment can include a terminal device, an AP (access point) for communicating with the terminal device according to a first (e.g., wireless LAN) protocol by using a first frequency band among multiple frequency bands of a prescribed frequency band (e.g., ISM frequency band) and a headset for communicating with the terminal device according to a second (e.g., Bluetooth) protocol by using at least one frequency band of remaining frequency bands by excepting the first frequency band.

摘要翻译： 应用的方法和系统的实施例可以使用无线LAN和蓝牙传输数据（例如，语音）。 一个系统实施例可以包括终端设备，用于根据第一（例如无线LAN）协议与终端设备进行通信的AP（接入点），该协议通过使用规定频带的多个频带中的第一频带（例如， ISM频带）和耳机，用于通过除了第一频带之外使用剩余频带的至少一个频带，根据第二（例如，蓝牙）协议与终端设备进行通信。

公开(公告)号：US06930560B2

公开(公告)日：2005-08-16

申请号：US10183974

申请日：2002-06-25

申请人： Kyeongho Lee ,  Deog-kyoon Jeong

发明人： Kyeongho Lee ,  Deog-kyoon Jeong

IPC分类号： H03K5/26 ,  H03L7/089 ,  H03L7/00

CPC分类号： H03L7/0891

摘要： A phase lock loop includes a charge pump, a voltage controlled oscillator (VCO), and a phase frequency detector. The phase frequency detector has a dynamic logic structure. The phase frequency detector generates up and down signals for directing the charge pump to provide a voltage signal to the VCO to vary the frequency of the VCO clock. The difference between the up and down signals is indicative of the phase difference between the reference clock signal and the VCO clock. The phase frequency detector includes up and down signal generators for generating the up and down signals, respectively.

摘要翻译： 锁相环包括电荷泵，压控振荡器（VCO）和相位频率检测器。 相位频率检测器具有动态逻辑结构。 相位频率检测器产生用于引导电荷泵的上升和下降信号以向VCO提供电压信号以改变VCO时钟的频率。 上升和下降信号之间的差异表示参考时钟信号和VCO时钟之间的相位差。 相位频率检测器包括分别产生上下信号的上下信号发生器。

公开(公告)号：US06512408B2

公开(公告)日：2003-01-28

申请号：US09985897

申请日：2001-11-06

申请人： Kyeongho Lee ,  Deog-Kyoon Jeong

发明人： Kyeongho Lee ,  Deog-Kyoon Jeong

IPC分类号： G06F744

CPC分类号： H04B1/40 ,  H03D7/1441 ,  H03F2200/372 ,  H03H11/22 ,  H03H2011/0494 ,  H03K9/00 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/1974 ,  H04B1/28 ,  H04B1/403

摘要： A mixer structure and method for using same in accordance with the present invention includes a multi-phase mixer. A VCO includes a plurality of differential delay cells to output a plurality of multi-phase clock signals. The multi-phase mixer can include a load circuit, switch circuit, noise reduction circuit and an input circuit. The switch circuit is coupled to receive the plurality of multi-phase clock signals and includes a first switch array and a second switch array coupled to the load circuit, respectively. The noise reduction circuit coupled to the switch circuit can include a transistor responsive to a bias voltage. The input circuit includes a transistor receiving the input signal. The first switch array includes a first plurality of switches coupled between a first output terminal and a second node, and the second switch array includes a second plurality of switches coupled between a second output terminal and the second node. Preferably, each of the plurality of switches includes two pairs of serially connected transistors, wherein the serially connected transistors are coupled in parallel to provide a symmetric electrical connection for each of two input ports. The mixer and method for using same can be single or double-balanced mixers receiving an RF input signal.

公开(公告)号：US06326826B1

公开(公告)日：2001-12-04

申请号：US09574571

申请日：2000-05-17

申请人： Kyeongho Lee ,  Deog-Kyoon Jeong

发明人： Kyeongho Lee ,  Deog-Kyoon Jeong

IPC分类号： H03L700

CPC分类号： H03L7/087 ,  H03L7/0812 ,  H03L7/0891 ,  H03L7/10 ,  H03L2207/14

摘要： A delay-locked loop (DLL), including frequency detection logic and a phase detector, is described having an operating range as wide as a conventional charge pump phase locked loop. The frequency detector logic counts the number of rising edges of the multi-phase clocks generated from a reference clock during one period of the reference clock. A loop filter is used to adjust the frequency of each multi-phase clock until frequency lock is obtained by comparing the number of rising edges. After frequency lock, phase detection logic is used to finely tune out the remaining phase error.

摘要翻译： 描述了包括频率检测逻辑和相位检测器的延迟锁定环（DLL），其具有与常规电荷泵锁相环一样​​宽的操作范围。 频率检测器逻辑计算在参考时钟的一个周期期间从参考时钟产生的多相时钟的上升沿的数量。 环路滤波器用于调整每个多相时钟的频率，直到通过比较上升沿的数量获得频率锁定为止。 在频率锁定之后，相位检测逻辑用于微调剩余的相位误差。

公开(公告)号：US6157263A

公开(公告)日：2000-12-05

申请号：US98266

申请日：1998-06-16

申请人： Kyeongho Lee ,  Deog-kyoon Jeong

发明人： Kyeongho Lee ,  Deog-kyoon Jeong

IPC分类号： H03K5/26 ,  H03L7/089 ,  H03L7/00

CPC分类号： H03L7/0891

摘要： A phase lock loop includes a charge pump, a voltage controlled oscillator (VCO), and a phase frequency detector. The phase frequency detector has a dynamic logic structure. The phase frequency detector generates up and down signals for directing the charge pump to provide a voltage signal to the VCO to vary the frequency of the VCO clock. The difference between the up and down signals is indicative of the phase difference between the reference clock signal and the VCO clock. The phase frequency detector includes up and down signal generators for generating the up and down signals, respectively. The up signal generator includes a first p field effect transistor (FET) having a gate for receiving a set signal, a second p FET having a source coupled to the drain of the first p FET and having a gate for receiving a reference clock signal. A first n FET has a source coupled to the drain of the second p FET and has a gate for receiving the set signal. A third p FET has a gate coupled to the drain of the second p FET. A second n FET has a source coupled to the drain of the third p FET for providing the up signal, and has a gate for receiving the reference clock signal. A third n FET has a source coupled to the drain of the second n FET and has a gate coupled to the gate of the third p FET. The down signal generator includes a fourth p FET having a gate for receiving the set signal. A fifth p FET has a source coupled to the drain of the fourth p FET and has a gate for receiving a VCO clock signal. A fourth n FET has a source coupled to the drain of the fifth n FET and has a gate for receiving the set signal. A sixth p FET has a gate coupled to the drain of the fifth p FET. A fifth n FET has a source coupled to the drain of the sixth p FET and has a gate for receiving the VCO clock signal. A sixth n FET has a source coupled to the drain of the fifth n FET for providing the down signal, and has a gate coupled to the gate of the sixth p FET. A reset circuit, such as a NAND gate, has a first input coupled to the drain of the third p FET, has a second input coupled to the drain of the sixth p FET, and has an output for generating the set signal.

公开(公告)号：US5825824A

公开(公告)日：1998-10-20

申请号：US622810

申请日：1996-03-27

申请人： Kyeongho Lee ,  Deog-Kyon Jeong

发明人： Kyeongho Lee ,  Deog-Kyon Jeong

IPC分类号： H03M7/14 ,  H03M5/14 ,  H04L7/00 ,  H04L7/04 ,  H04L25/03 ,  H04L25/08 ,  H04L25/49 ,  H04N7/083 ,  H04N7/52 ,  H04N21/2368 ,  H04N21/434 ,  H04L25/34 ,  H03M5/00 ,  H04J3/24

CPC分类号： H04L25/085 ,  H04L25/03866 ,  H04L25/4915 ,  H04N21/2368 ,  H04N21/4341 ,  H04N7/083 ,  H04N7/52 ,  H04L2007/045 ,  H04L7/0008

摘要： A method and apparatus for producing a transition-controlled, DC-balanced sequence of characters from an input sequence of data bytes. The bits in each of the data bytes are selectively complemented in accordance with the number of logical `1` signals in each data byte in order to produce selectively complemented data blocks. A cumulative disparity is then determined between the logical values of different type included within ones of the selectively complemented data blocks previously encoded into characters. In addition, a current disparity in a candidate character associated with a current one of the selectively complemented data blocks being encoded is also determined. The candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of a polarity opposite to a first polarity of the cumulative disparity. Alternately, the complement of the candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of the first polarity. In a high-transition mode of operation, the bits within data blocks including fewer than a minimum number of logical `1` signals are selectively complemented so that each such selectively complemented data block includes in excess of the minimum number of logical transitions. In a low-transition mode of operation, the bits within data blocks having more than a predefined number of logical `1` signals are selectively complemented so that each such selectively complemented data block includes less than the maximum number of logical transitions.

摘要翻译： 一种用于从数据字节的输入序列产生转换控制的直流平衡字符序列的方法和装置。 每个数据字节中的位根据每个数据字节中的逻辑“1”信号的数目选择性地补充，以便产生选择性补充的数据块。 然后在包括在先前编码为字符的选择性补充的数据块中的不同类型的逻辑值之前确定累积差异。 此外，还确定与被编码的选择性补充的数据块中的当前一个相关联的候选字符中的当前差异。 如果当前视差与累积视差的第一极性相反的极性，则候选字符被分配给选择性补充的数据块中的当前一个。 或者，如果当前视差是第一极性，则候选字符的补码被分配给选择性补充的数据块中的当前一个。 在高转换操作模式中，选择性地补充包括少于最小数量的逻辑“1”信号的数据块内的位，使得每个这样的选择性补充的数据块包括超过最小数量的逻辑转换。 在低转换操作模式中，选择性地补充具有超过预定数量的逻辑“1”信号的数据块内的位，使得每个这样的选择性补充的数据块包括小于逻辑转换的最大数量。

公开(公告)号：US07606293B2

公开(公告)日：2009-10-20

申请号：US10690629

申请日：2003-10-23

申请人： Byoung-Hoon Kim ,  Suwon Kang ,  Bong Youl Cho ,  Kyeongho Lee

发明人： Byoung-Hoon Kim ,  Suwon Kang ,  Bong Youl Cho ,  Kyeongho Lee

IPC分类号： H04B1/00

CPC分类号： H04B1/7097 ,  H04B1/7115 ,  H04L25/03171

摘要： A bidirectional turbo ISI canceller cancels precursor-ISI as well as postcursor-ISI in a received signal without incorporating a multiplicative feedforward equalization filter. This is accomplished by taking a three-step receiver design approach. In the first step, an optimal single-symbol RAKE receiver is designed to comprise a CMF, a codeword correlator bank, and an energy bias (EB) canceller under the assumption that no ISI is generated by preceding or trailing symbols. In a second step, a DFE is included for suppressing postcursor-ISI caused by a preceding symbol. Finally, a precursor ISI canceler is used to remove the remaining ISI caused by a trailing symbol. All three components may be integrated into a BTIC-based receiver applying turbo-iteration processing.

摘要翻译： 双向turbo ISI消除器在接收信号中取消前体ISI以及后端ISI，而不需要并入前置均衡滤波器。 这是通过采取三步接收机设计方法来实现的。 在第一步中，假定不存在由先前或后面符号产生的ISI，最佳单符号RAKE接收机被设计为包括CMF，码字相关器组和能量偏置（EB）消除器。 在第二步骤中，包括用于抑制由先前符号引起的后期ISI的DFE。 最后，使用前驱体ISI消除器去除由尾随符号引起的剩余ISI。 所有三个组件可以被集成到应用turbo迭代处理的基于BTIC的接收机中。