公开(公告)号：US07688126B2

公开(公告)日：2010-03-30

申请号：US12362247

申请日：2009-01-29

Applicant: Stephan Henzler ,  Siegmar Köppe ,  Dominik Lorenz

Inventor： Stephan Henzler ,  Siegmar Köppe ,  Dominik Lorenz

IPC: H03H11/26

CPC classification number: H03K5/13 ,  G04F10/06 ,  H03K5/135 ,  H03L7/085 ,  H03M1/205

Abstract: A time delay circuit is disclosed and includes a delay line with a first delay circuit and at least a second delay circuit connected downstream. An interpolation circuit is used to generate intermediate signals derived by delayed successive signals in the delay line.

Abstract translation: 公开了一种延时电路，并且包括具有第一延迟电路和至少连接在下游的第二延迟电路的延迟线。 内插电路用于产生由延迟线中延迟的连续信号导出的中间信号。

公开(公告)号：US20090293629A1

公开(公告)日：2009-12-03

申请号：US12305599

申请日：2008-01-09

Applicant: Stephan Henzler ,  Tobby Brandt ,  Christian Ohl ,  Boris Adam ,  Martin Schuerer

Inventor： Stephan Henzler ,  Tobby Brandt ,  Christian Ohl ,  Boris Adam ,  Martin Schuerer

IPC: G01L7/00

CPC classification number: B60R11/00 ,  B60R13/06 ,  B60R2011/0052 ,  B60R2021/0006 ,  B60R2021/01006

Abstract: An air pressure sensor for sensing a side impact includes fastening means for fastening the air pressure sensor on a vehicle wall, the fastening means having a single aperture for accommodating a single fastening element, the fastening element being used for fastening the air pressure sensor on the vehicle wall. Furthermore, the fastening means have a structure on the pressure inlet channel which passes through an aperture in the vehicle door. The at least one structure is shaped in such a way that the at least one structure makes it possible for the air pressure sensor to be hooked on the vehicle wall.

Abstract translation: 用于感测侧面碰撞的空气压力传感器包括用于将空气压力传感器紧固在车辆壁上的紧固装置，所述紧固装置具有用于容纳单个紧固元件的单个孔，该紧固元件用于将空气压力传感器紧固在 车墙。 此外，紧固装置在通过车门的孔的压力入口通道上具有结构。 至少一个结构被成形为使得至少一个结构使空气压力传感器可以钩在车辆壁上。

公开(公告)号：US20090257319A1

公开(公告)日：2009-10-15

申请号：US12101814

申请日：2008-04-11

Applicant: Stephan Henzler

Inventor： Stephan Henzler

IPC: G04F10/00 ,  H03L7/00

CPC classification number: G04F10/04

Abstract: A device is dislosed for measuring a plurality of time intervals.

Abstract translation: 用于测量多个时间间隔的装置被关闭。

公开(公告)号：US20090072812A1

公开(公告)日：2009-03-19

申请号：US11855415

申请日：2007-09-14

Applicant: Stephan Henzler ,  Matthias Schobinger

Inventor： Stephan Henzler ,  Matthias Schobinger

IPC: G01R13/02

CPC classification number: G04F10/00 ,  G04F10/005

Abstract: An apparatus including a circuit configured to measure timing between features in a first signal only referring to timing information contained in the signal itself.

Abstract translation: 一种装置，包括被配置为仅参照包含在信号本身中的定时信息来测量第一信号中的特征之间的定时的电路。

公开(公告)号：US07411423B2

公开(公告)日：2008-08-12

申请号：US11194495

申请日：2005-08-01

Applicant: Jörg Berthold ,  Georg Georgakos ,  Stephan Henzler ,  Doris Schmitt-Landsiedel

Inventor： Jörg Berthold ,  Georg Georgakos ,  Stephan Henzler ,  Doris Schmitt-Landsiedel

IPC: H03K19/096

CPC classification number: H03K19/0016

Abstract: Logic activation circuit for switching a logic circuit having at least one supply voltage line on or off, said logic activation circuit having: (a) at least one voltage supply switching device for connecting a supply voltage to a supply voltage line of the logic circuit in a manner dependent on a changeover control signal that is applied to a control terminal of the voltage supply switching device; and having (b) a charge equalization switching device which, in a manner dependent on a control switching pulse, connects the supply voltage line of the logic circuit to the control terminal of the voltage supply switching device for the duration of the control switching pulse so that charge equalization is effected between the supply voltage line and the control terminal of the voltage supply switching device in order to generate the changeover control signal.

Abstract translation: 逻辑启动电路，用于切换具有至少一个电源电压线的逻辑电路，所述逻辑启动电路具有：（a）至少一个电压供应切换装置，用于将电源电压连接到逻辑电路的电源电压线 取决于施加到电压切换装置的控制端的切换控制信号的方式; 并且具有（b）电荷均衡切换装置，其以取决于控制切换脉冲的方式，在控制切换脉冲的持续时间内将逻辑电路的电源电压线连接到电源开关装置的控制端子 在电源电压线和电源切换装置的控制端之间进行充电均衡，以产生转换控制信号。

公开(公告)号：US20060273838A1

公开(公告)日：2006-12-07

申请号：US10563040

申请日：2004-09-03

Applicant: Jorg Berthold ,  Georg Jeorgakos ,  Stephan Henzler ,  Doris Schmitt-Landsiedel

Inventor： Jorg Berthold ,  Georg Jeorgakos ,  Stephan Henzler ,  Doris Schmitt-Landsiedel

IPC: H03H11/26

CPC classification number: H03K3/037 ,  H03K3/356121

Abstract: A master latch circuit (10) with signal level displacement for a flip-flop (1) clocked by a clock pulse signal (Clk), wherein the master latch circuit (10) comprises a signal delay circuit (13) which delays and inverts the clock pulse signal (ClK) resulting in a specific time delay (AT), and a circuit node (14) which, in a charging phase wherein the clock pulse signal (Clk) is logically low, is charged to an operational voltage (VB) an which, in an evaluation phase when the clock pulse signal (Clk) and delayed, inverted clock pulse signal (Clk DELAY ) are logically high, is discharged according to a specific data signal (D), wherein the data signal controls only transistors of a single type (either only N-channel or only P-channel). The master latch circuit (10) has only one supply voltage.

Abstract translation: 一种具有由时钟脉冲信号（Clk）时钟的触发器（1）的信号电平位移的主锁存电路（10），其中主锁存电路（10）包括信号延迟电路（13），其延迟和反相 导致特定时间延迟（AT）的时钟脉冲信号（ClK）和在时钟脉冲信号（Clk）在逻辑上低的充电阶段被充电到工作电压（VB）的电路节点（14） 当在时钟脉冲信号（Clk）和延迟的反相时钟脉冲信号（Clk DELAY ）在逻辑上为高时，在根据特定数据信号（D）放电的评估阶段中， 数据信号仅控制单一类型的晶体管（仅N沟道或仅P通道）。 主锁存电路（10）只有一个电源电压。

公开(公告)号：US20060119406A1

公开(公告)日：2006-06-08

申请号：US11274048

申请日：2005-11-15

Applicant: Stephan Henzler ,  Joerg Berthold ,  Georg Georgakos ,  Doris Schmitt-Landsiedel ,  Christian Pacha

Inventor： Stephan Henzler ,  Joerg Berthold ,  Georg Georgakos ,  Doris Schmitt-Landsiedel ,  Christian Pacha

IPC: H03K3/356

CPC classification number: G11C11/412

Abstract: The flip-flop according to the invention serves for storing an item of logic state information and has at least one data input and at least one data output. The flip-flop comprises at least one latch stage for storing the state information if the flip-flop is switched on. Furthermore, the flip-flop according to the invention comprises at least one memory cell having a capacitance as storage element. In this case, the at least one memory cell serves for storing the state information if the flip-flop is switched off.

Abstract translation: 根据本发明的触发器用于存储一个逻辑状态信息项，并具有至少一个数据输入和至少一个数据输出。 如果触发器被接通，触发器包括用于存储状态信息的至少一个锁存级。 此外，根据本发明的触发器包括具有作为存储元件的电容的至少一个存储单元。 在这种情况下，如果触发器被关闭，则至少一个存储单元用于存储状态信息。

公开(公告)号：US20060022712A1

公开(公告)日：2006-02-02

申请号：US11194495

申请日：2005-08-01

Applicant: Jorg Berthold ,  Georg Georgakos ,  Stephan Henzler ,  Doris Schmitt-Landsiedel

Inventor： Jorg Berthold ,  Georg Georgakos ,  Stephan Henzler ,  Doris Schmitt-Landsiedel

IPC: H03K19/094

CPC classification number: H03K19/0016

Abstract: Logic activation circuit for switching a logic circuit having at least one supply voltage line on or off, said logic activation circuit having: (a) at least one voltage supply switching device for connecting a supply voltage to a supply voltage line of the logic circuit in a manner dependent on a changeover control signal that is applied to a control terminal of the voltage supply switching device; and having (b) a charge equalization switching device which, in a manner dependent on a control switching pulse, connects the supply voltage line of the logic circuit to the control terminal of the voltage supply switching device for the duration of the control switching pulse so that charge equalization is effected between the supply voltage line and the control terminal of the voltage supply switching device in order to generate the changeover control signal.

Abstract translation: 逻辑启动电路，用于切换具有至少一个电源电压线的逻辑电路，所述逻辑启动电路具有：（a）至少一个电压供应切换装置，用于将电源电压连接到逻辑电路的电源电压线 取决于施加到电压切换装置的控制端的切换控制信号的方式; 并且具有（b）电荷均衡切换装置，其以取决于控制切换脉冲的方式，在控制切换脉冲的持续时间内将逻辑电路的电源电压线连接到电源开关装置的控制端子 在电源电压线和电源切换装置的控制端之间进行充电均衡，以产生转换控制信号。