公开(公告)号：US07772643B2

公开(公告)日：2010-08-10

申请号：US12457323

申请日：2009-06-08

申请人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

发明人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

IPC分类号： H01L29/94 ,  H01L29/78

CPC分类号： H01L21/823437 ,  H01L21/28247 ,  H01L29/4941 ,  H01L29/6656

摘要： A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).

摘要翻译： 提供一种制造具有金属栅极图案的半导体器件的方法，其中使用覆盖层来控制氧化过程中金属栅极图案的部分的相对氧化率。 覆盖层可以是多层结构，并且可以被蚀刻以在金属栅极图案的侧壁上形成绝缘间隔物。 封盖层允许使用选择性氧化工艺，其可以是在富H2气氛中使用H 2 O和H 2的分压的湿式氧化工艺，以氧化基板和金属栅极图案的部分，同时抑制 可以包括在金属栅极图案中的金属层的氧化。 这允许对硅衬底的蚀刻损伤和金属栅极图案的边缘减小，同时基本上保持栅极绝缘层的原始厚度和金属层的导电性。

公开(公告)号：US20100184449A1

公开(公告)日：2010-07-22

申请号：US12657321

申请日：2010-01-19

申请人： Sung-Man Kim ,  Jun-Sung Lee ,  Seong-Yong Park

发明人： Sung-Man Kim ,  Jun-Sung Lee ,  Seong-Yong Park

IPC分类号： H04W72/04

CPC分类号： H04B17/21

摘要： A base station is capable of performing 4-beamforming using Radio Units (RU), each having two paths in a wireless communication system. The base station includes a Digital Unit (DU), a first RU, and a second RU. The DU performs a mutual conversion function between an information bit line and a digital signal, calculates beamforming coefficients for 4-beamforming, and performs the 4-beamforming using the beamforming coefficients. The first RU has two Radio Frequency (RF) paths, extracts a clock signal from a digital signal from the DU, and provides the clock signal to the second RU. The second RU has two RF paths and operates according to the clock signal provided from the first RU.

摘要翻译： 基站能够使用无线电单元（RU）来执行四波束成形，每个单元在无线通信系统中具有两条路径。 基站包括数字单元（DU），第​​一RU和第二RU。 DU在信息位线和数字信号之间执行相互转换功能，计算4波束成形的波束形成系数，并使用波束成形系数执行4波束成形。 第一RU具有两个射频（RF）路径，从DU的数字信号中提取时钟信号，并将时钟信号提供给第二RU。 第二RU具有两个RF路径，并且根据从第一RU提供的时钟信号进行操作。

公开(公告)号：US20100064936A1

公开(公告)日：2010-03-18

申请号：US12513296

申请日：2007-11-01

申请人： Sung-Man Kim

发明人： Sung-Man Kim

IPC分类号： C09D103/02

CPC分类号： C08L3/00 ,  C08K5/098 ,  C08L3/06 ,  C08L91/06 ,  C08L2205/02

摘要： This invention relates to a non-sulfurous statuary material and a method of manufacturing the same, and particularly, to a novel statuary material containing no sulfur, which is capable of substituting for a conventional statuary material containing sulfur as a component of a statuary filling composition, in particular, an industrial statuary material, and to a method of manufacturing the same. In the case where the statuary material according to this invention is used, because it contains no sulfur, unlike conventional statuary material, environmental contamination and the generation of offensive odors due to sulfur are avoided, and furthermore, the use of material having a specific gravity lower than that of sulfur facilitates modeling.

摘要翻译： 本发明涉及一种非硫磺雕像材料及其制造方法，特别涉及一种不含硫的新型雕像材料，其能够代替含有硫的常规雕刻材料作为雕塑填充组合物的组分 特别是工业雕塑材料及其制造方法。 在使用根据本发明的雕刻材料的情况下，由于不含硫，因此与常规雕刻材料不同，避免了环境污染和由于硫而引起的恶臭的产生，此外，使用具有比重的材料 低于硫，有利于建模。

公开(公告)号：US07655952B2

公开(公告)日：2010-02-02

申请号：US11770012

申请日：2007-06-28

申请人： Hye-Young Ryu ,  Young-Hoon Yoo ,  Jang-Soo Kim ,  Sung-Man Kim ,  Kyung-Wook Kim ,  Hyang-Shik Kong ,  Young-Goo Song

发明人： Hye-Young Ryu ,  Young-Hoon Yoo ,  Jang-Soo Kim ,  Sung-Man Kim ,  Kyung-Wook Kim ,  Hyang-Shik Kong ,  Young-Goo Song

IPC分类号： H01L33/00

CPC分类号： G02F1/136227 ,  G02F2001/136236 ,  H01L27/1244 ,  H01L27/1248

摘要： A thin film transistor array panel is provided, which includes: a gate line, a gate insulating layer, and a semiconductor layer sequentially formed on a substrate; a data line and a drain electrode formed at least on the semiconductor layer; a first passivation layer formed on the data line and the drain electrode and having a first contact hole exposing the drain electrode at least in part; a second passivation layer formed on the first passivation layer and having a second contact hole that is disposed on the first contact hole and has a first bottom edge, placed outside the first contact hole and a second bottom edge placed inside the first contact hole; and a pixel electrode formed on the second passivation layer and connected to the drain electrode through the first and the second contact holes.

摘要翻译： 提供薄膜晶体管阵列面板，其包括：顺序地形成在基板上的栅极线，栅极绝缘层和半导体层; 至少形成在所述半导体层上的数据线和漏电极; 形成在所述数据线和所述漏电极上的第一钝化层，并且具有至少部分地暴露所述漏电极的第一接触孔; 第二钝化层，其形成在所述第一钝化层上，并且具有设置在所述第一接触孔上并且具有放置在所述第一接触孔外部的第一底部边缘的第二接触孔和放置在所述第一接触孔内部的第二底部边缘; 以及形成在所述第二钝化层上并通过所述第一和第二接触孔连接到所述漏电极的像素电极。

公开(公告)号：US07306996B2

公开(公告)日：2007-12-11

申请号：US11498197

申请日：2006-08-03

申请人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

发明人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

IPC分类号： H01L21/336 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/823437 ,  H01L21/28247 ,  H01L29/4941 ,  H01L29/6656

摘要： A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).

摘要翻译： 提供一种制造具有金属栅极图案的半导体器件的方法，其中使用覆盖层来控制氧化过程中金属栅极图案的部分的相对氧化率。 覆盖层可以是多层结构，并且可以被蚀刻以在金属栅极图案的侧壁上形成绝缘间隔物。 封盖层允许使用选择性氧化工艺，其可以是使用H 2 H 2 O和H 2 H 2的分压的H氧化方法 2极化气氛，以便在抑制可能包含在金属栅极图案中的金属层的氧化的同时氧化基板和金属栅极图案的部分。 这允许对硅衬底的蚀刻损伤和金属栅极图案的边缘减小，同时基本上保持栅极绝缘层的原始厚度和金属层的导电性。

公开(公告)号：US20060270204A1

公开(公告)日：2006-11-30

申请号：US11498195

申请日：2006-08-03

申请人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

发明人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

IPC分类号： H01L21/4763 ,  H01L21/3205

CPC分类号： H01L21/823437 ,  H01L21/28247 ,  H01L29/4941 ,  H01L29/6656

摘要： A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).

摘要翻译： 提供一种制造具有金属栅极图案的半导体器件的方法，其中使用覆盖层来控制氧化过程中金属栅极图案的部分的相对氧化率。 覆盖层可以是多层结构，并且可以被蚀刻以在金属栅极图案的侧壁上形成绝缘间隔物。 封盖层允许使用选择性氧化工艺，其可以是使用H 2 H 2 O和H 2 H 2的分压的H氧化方法 2极化气氛，以便在抑制可能包含在金属栅极图案中的金属层的氧化的同时氧化基板和金属栅极图案的部分。 这允许对硅衬底的蚀刻损伤和金属栅极图案的边缘减小，同时基本上保持栅极绝缘层的原始厚度和金属层的导电性。

公开(公告)号：US20060164350A1

公开(公告)日：2006-07-27

申请号：US11312680

申请日：2005-12-19

申请人： Sung-Man Kim ,  Seong-Young Lee ,  Beom-Jun Kim ,  Seung Moon ,  Hyang-Shik Kong

发明人： Sung-Man Kim ,  Seong-Young Lee ,  Beom-Jun Kim ,  Seung Moon ,  Hyang-Shik Kong

IPC分类号： G09G3/36

CPC分类号： G09G3/3614 ,  G02F1/1345 ,  G02F2201/40 ,  G09G3/3648 ,  G09G2300/0426 ,  G09G2300/0443

摘要： Disclosed is a thin film transistor array panel. The panel includes a plurality of pixels arranged in the form of a matrix each with a pixel electrode and a switching element connected to the pixel electrode, and a plurality of gate lines connected to the switching elements and extending in the row direction. A pair of the gate lines are connected to pixels in each pixel row. A plurality of data lines are connected to the switching elements, and elongated in the column direction. Each data line is provided between two columns of the pixels. The respective data lines are horizontally bent between the two adjacent gate lines, and vertically extend between the two pixel rows.

摘要翻译： 公开了一种薄膜晶体管阵列面板。 面板包括以矩阵形式布置的多个像素，每个像素连接有像素电极和连接到像素电极的开关元件，以及连接到开关元件并沿行方向延伸的多条栅极线。 一对栅极线连接到每个像素行中的像素。 多个数据线连接到开关元件，并且在列方向上延伸。 每个数据线都在两列像素之间提供。 相应的数据线在两个相邻的栅极线之间水平弯曲，并且在两个像素行之间垂直延伸。

公开(公告)号：US20050062046A1

公开(公告)日：2005-03-24

申请号：US10902251

申请日：2004-07-29

申请人： Sung-Man Kim ,  Young-Goo Song ,  Hyang-Shik Kong ,  Dong-Hyun Ki ,  Seong-Young Lee ,  Joo-Ae Yoon ,  Jong-Woong Chang

发明人： Sung-Man Kim ,  Young-Goo Song ,  Hyang-Shik Kong ,  Dong-Hyun Ki ,  Seong-Young Lee ,  Joo-Ae Yoon ,  Jong-Woong Chang

IPC分类号： G02F1/1333 ,  G02F1/1345 ,  G02F1/1362 ,  G02F1/1368 ,  G09F9/30 ,  H01L21/77 ,  H01L21/84 ,  H01L27/01 ,  H01L27/12 ,  H01L27/32 ,  H01L29/45 ,  H01L29/49 ,  H01L29/22

CPC分类号： H01L27/016 ,  G02F1/13458 ,  G02F1/136227 ,  H01L27/12 ,  H01L27/1244 ,  H01L27/1248 ,  H01L27/1288 ,  H01L27/3244 ,  H01L29/456 ,  H01L29/4908

摘要： A thin film array panel is provided, which includes: a plurality of signal lines including contact parts for contact with an external device; a plurality of thin film transistors connected to the signal lines; an insulating layer formed on the signal lines and the thin film transistors; and a plurality of pixel electrodes formed on the insulating layer and connected to the thin film transistors, wherein the insulating layer includes a contact portion disposed on the contact parts of the signal lines and having a thickness smaller than other portions and the contact portion of the insulating layer includes an inclined portion having an inclination angle smaller than about 45 degrees.

摘要翻译： 提供一种薄膜阵列面板，其包括：多条信号线，包括用于与外部装置接触的接触部分; 连接到信号线的多个薄膜晶体管; 形成在信号线和薄膜晶体管上的绝缘层; 以及形成在所述绝缘层上并连接到所述薄膜晶体管的多个像素电极，其中所述绝缘层包括设置在所述信号线的接触部分上并具有小于其它部分的厚度的接触部分，并且所述接触部分 绝缘层包括具有小于约45度的倾斜角度的倾斜部分。

公开(公告)号：US06864132B2

公开(公告)日：2005-03-08

申请号：US10373005

申请日：2003-02-24

申请人： Jun-Kyu Cho ,  Si-Young Choi ,  Sun-Pil Youn ,  Sung-Man Kim ,  Ja-Hum Ku

发明人： Jun-Kyu Cho ,  Si-Young Choi ,  Sun-Pil Youn ,  Sung-Man Kim ,  Ja-Hum Ku

IPC分类号： H01L21/3213 ,  H01L21/28 ,  H01L29/51 ,  H01L21/8234

CPC分类号： H01L29/518 ,  H01L21/28061 ,  H01L21/28176 ,  H01L21/28247

摘要： Integrated circuit gates are fabricated by forming an insulated gate on an integrated circuit substrate, wherein the insulated gate includes a gate oxide on the integrated circuit substrate, a polysilicon pattern including polysilicon sidewalls, on the gate oxide, and a metal pattern on the polysilicon pattern. The insulated gate is pretreated with hydrogen and nitrogen gasses. The polysilicon sidewalls are then oxidized. The pretreating in hydrogen and nitrogen gasses prior to oxidizing can reduce growth in thickness of the gate oxide during the oxidizing and/or can reduce formation of whiskers on the metal pattern, compared to absence of the pretreatment.

摘要翻译： 通过在集成电路基板上形成绝缘栅极来制造集成电路栅极，其中绝缘栅极包括在集成电路基板上的栅极氧化物，在栅极氧化物上包括多晶硅侧壁的多晶硅图案，以及多晶硅图案上的金属图案 。 绝缘栅极用氢气和氮气预处理。 然后将多晶硅侧壁氧化。 在氧化之前在氢气和氮气中预处理可以减少在氧化期间栅极氧化物的厚度增长和/或可以减少与不进行预处理相比在金属图案上形成晶须。

公开(公告)号：US09257455B2

公开(公告)日：2016-02-09

申请号：US13288893

申请日：2011-11-03

申请人： Bon-Yong Koo ,  Sung-Man Kim ,  Jae-Hoon Lee

发明人： Bon-Yong Koo ,  Sung-Man Kim ,  Jae-Hoon Lee

IPC分类号： G09G3/36 ,  H01L27/12 ,  H01L29/417

CPC分类号： H01L27/1259 ,  G09G3/3611 ,  H01L27/1255 ,  H01L29/41733

摘要： A gate drive circuit includes plural stages connected together one after each other. Each of the plural stages includes a circuit transistor, a capacitor part, a first connection part and a second connection part. The circuit transistor outputs the gate signal through a source electrode in response to a control signal applied through a gate electrode. The capacitor part includes a first electrode, a second electrode formed on the first electrode, and a third electrode formed on the second electrode. The first connection part electrically connects the gate electrode of the circuit transistor and the second electrode of the capacitor part. The second connection part electrically connects the source electrode of the circuit transistor and the first electrode of the capacitor part. Thus, an integrated size of a gate drive circuit may be decreased, and a reliability of a gate drive circuit may be enhanced.

摘要翻译： 栅极驱动电路包括一个接一个地连接在一起的多个级。 多级中的每一个包括电路晶体管，电容器部分，第一连接部分和第二连接部分。 响应于通过栅电极施加的控制信号，电路晶体管通过源电极输出栅极信号。 电容器部分包括第一电极，形成在第一电极上的第二电极和形成在第二电极上的第三电极。 第一连接部电连接电路晶体管的栅电极和电容器部的第二电极。 第二连接部分电连接电路晶体管的源电极和电容器部分的第一电极。 因此，可以减小栅极驱动电路的集成尺寸，并且可以提高栅极驱动电路的可靠性。