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    Flexible hybrid firewall architecture
    74.
    发明授权
    Flexible hybrid firewall architecture 有权

    公开(公告)号：US11212256B2

    公开(公告)日：2021-12-28

    申请号：US16786734

    申请日：2020-02-10

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Amritpal Singh Mundra ,  Brian J. Karguth ,  Timothy Anderson ,  Kai Chirca ,  Charles Fuoco

    IPC: H04L29/06

    Abstract: A flexible hybrid firewall architecture is disclosed. A system implementing such an architecture includes an access control register, a memory having at least a region to which access is controllable by the access control register, the access control register including first field that contains a privilege identifier (ID) and a plurality of additional fields, each additional field containing control bits corresponding to a respective one of a plurality of permission levels, and control circuitry that, in response to receiving a transaction containing a transaction privilege ID, a security indicator, and a privilege indicator, controls access to the region when the transaction privilege ID matches the privilege ID contained in the first field by using the control bits of a field of the additional fields that corresponds to a security level indicated by the security indicator and a privilege level indicated by the privilege indicator of the transaction.

    NESTED LOOP CONTROL
    75.
    发明申请
    NESTED LOOP CONTROL 有权

    公开(公告)号：US20210334103A1

    公开(公告)日：2021-10-28

    申请号：US17367384

    申请日：2021-07-04

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Kai Chirca ,  Timothy D. Anderson ,  Todd T. Hahn ,  Alan L. Davis

    IPC: G06F9/30

    Abstract: A nested loop controller includes a first register having a first value initialized to an initial first value, a second register having a second value initialized to an initial second value, and a third register configured as a predicate FIFO, initialized to have a third value. The second value is advanced in response to a tick instruction during execution of a loop. In response to the second value reaching a second threshold, the second register is reset to the initial second value. The nested loop controller further includes a comparator coupled to the second register and to the predicate FIFO and configured to provide an outer loop indicator value as input to the predicate FIFO when the second value is equal to the second threshold, and provide an inner loop indicator value as input to the predicate FIFO when the second value is not equal to the second threshold.

    MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM
    77.
    发明申请
    MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM 审中-公开

    公开(公告)号：US20200371937A1

    公开(公告)日：2020-11-26

    申请号：US16879264

    申请日：2020-05-20

    Applicant: Texas Instruments Incorporated

    Inventor： Abhijeet Ashok Chachad ,  Timothy David Anderson ,  Kai Chirca ,  David Matthew Thompson

    IPC: G06F12/0842 ,  G06F12/0888 ,  G06F12/0811

    Abstract: In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.

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