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    Semiconductor die with conversion coating
    75.
    发明授权
    Semiconductor die with conversion coating 有权

    公开(公告)号：US11121076B2

    公开(公告)日：2021-09-14

    申请号：US16454847

    申请日：2019-06-27

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Nazila Dadvand ,  Christopher Daniel Manack

    IPC: H01L23/522 ,  H01L23/31 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L23/00

    Abstract: A die includes a semiconductor layer, an electrical contact on a first side of the semiconductor layer, a backside electrical contact layer on second side of the semiconductor layer. The die further includes a zinc layer over at least one of the electrical contact or the backside electrical contact layer of the die, and a conversion coating over the zinc layer. The conversion coating includes at least one of zirconium and vanadium. As part of an embedded die package including the die, at least a portion of the conversion coating may adjacent to an electrically insulating substrate of the embedded die package.

    Multi-pitch leads
    77.
    发明授权
    Multi-pitch leads 有权

    公开(公告)号：US11094616B2

    公开(公告)日：2021-08-17

    申请号：US16543238

    申请日：2019-08-16

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Sreenivasan K. Koduri ,  Nazila Dadvand

    IPC: H01L23/495 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  C25D7/00 ,  H01L23/31

    Abstract: In some examples, a system comprises a die having multiple electrical connectors extending from a surface of the die and a lead coupled to the multiple electrical connectors. The lead comprises a first conductive member; a first non-solder metal plating stacked on the first conductive member; an electroplated layer stacked on the first non-solder metal plating; a second non-solder metal plating stacked on the electroplated layer; and a second conductive member stacked on the second non-solder metal plating, the second conductive member being thinner than the first conductive member. The system also comprises a molding to at least partially encapsulate the die and the lead.

    NIckel Alloy for Semiconductor Packaging
    79.
    发明申请
    NIckel Alloy for Semiconductor Packaging 有权

    公开(公告)号：US20210242151A1

    公开(公告)日：2021-08-05

    申请号：US17234429

    申请日：2021-04-19

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Nazila Dadvand ,  Christopher Daniel Manack ,  Salvatore Frank Pavone

    IPC: H01L23/00 ,  H01L21/78

    Abstract: A packaged semiconductor die includes a semiconductor die coupled to a die pad. The semiconductor die has a front side containing copper leads, a copper seed layer coupled to the copper leads, and a nickel alloy coating coupled to the copper seed layer. The nickel alloy includes tungsten and cerium (NiWCe). The packaged semiconductor die may also include wire bonds coupled between leads of a lead frame and the copper leads of the semiconductor die. In addition, the packaged semiconductor die may be encapsulated in molding compound. A method for fabricating a packaged semiconductor die. The method includes forming a copper seed layer over the copper leads of the semiconductor die. In addition, the method includes coating the copper seed layer with a nickel alloy. The method also includes singulating the semiconductor wafer to create individual semiconductor die and placing the semiconductor die onto a die pad of a lead frame. In addition the method includes wire bonding the leads of a lead frame to the copper leads of the semiconductor die and then encapsulating the die in molding compound.

    SEMICONDUCTOR DEVICE WITH METAL DIE ATTACH TO SUBSTRATE WITH MULTI-SIZE CAVITY
    80.
    发明申请
    SEMICONDUCTOR DEVICE WITH METAL DIE ATTACH TO SUBSTRATE WITH MULTI-SIZE CAVITY 有权

    公开(公告)号：US20210125902A1

    公开(公告)日：2021-04-29

    申请号：US17142598

    申请日：2021-01-06

    Applicant: Texas Instruments Incorporated

    Inventor： Benjamin Stassen Cook ,  Nazila Dadvand ,  Sreenivasan Koduri

    IPC: H01L23/495 ,  H01L21/48

    Abstract: A semiconductor device includes a metal substrate including a through-hole aperture having a multi-size cavity including a larger area first cavity portion above a smaller area second cavity portion that defines a first ring around the second cavity portion, where the first cavity portion is sized with area dimensions to receive a semiconductor die having a top side with circuitry coupled to bond pads thereon and a back side with a metal (BSM) layer thereon. The semiconductor die is mounted top side up with the BSM layer on the first ring. A metal die attach layer directly contacts the BSM layer, sidewalls of the bottom cavity portion, and a bottom side of the metal substrate.

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