公开(公告)号：US11152468B2

公开(公告)日：2021-10-19

申请号：US16089421

申请日：2017-03-30

Applicant: Tohoku University

Inventor： Kunihiro Tsubomi ,  Tetsuo Endoh ,  Masakazu Muraguchi

IPC: H01L29/10 ,  H01L29/417 ,  H01L29/78 ,  H01L29/423 ,  H01L21/76 ,  H01L29/06

Abstract: Provided is a semiconductor device. A semiconductor device includes a substrate, a buffer layer provided on the substrate, a semiconductor layer provided on the buffer layer, a body region provided at a part of a surface layer of the semiconductor layer, a source region provided at a part of a surface layer of the body region, a drain region provided at a part of the surface layer of the semiconductor layer outside the body region, a gate insulating layer provided to extend from the surface layer of the body region to a predetermined depth, a gate electrode provided on the gate insulating layer, a source electrode provided on the source region, a drain electrode provided on the drain region, and an isolation region provided to extend from the surface layer of the semiconductor layer to above the predetermined depth.

公开(公告)号：US11133046B2

公开(公告)日：2021-09-28

申请号：US16339818

申请日：2017-10-31

Applicant: TOHOKU UNIVERSITY

Inventor： Takahiro Hanyu ,  Daisuke Suzuki ,  Hideo Ohno ,  Tetsuo Endoh

IPC: G11C11/16 ,  H01L43/02

Abstract: A data write device for a resistive memory element, the resistive memory element including: a conductive electrode provided at one end of the memory element; and a reading electrode provided at the other end of the memory element being configured to vary a resistance of the memory element by applying a write current to the conductive electrode, the data write device for the resistive memory element further includes: a writing means, an output means, and a control means. The output means is provided between a power supply and the reading electrode. As output signals, a read signal from the memory element and a monitor signal to monitor a writing status of the memory element written by the writing means are output from the output means. By the monitor signal, a termination of data-writing into the resistive memory element is detected.

公开(公告)号：US20210233577A1

公开(公告)日：2021-07-29

申请号：US17052749

申请日：2019-04-10

Applicant: TOHOKU UNIVERSITY

Inventor： Yoshiaki Saito ,  Shoji Ikeda ,  Tetsuo Endoh

IPC: G11C11/16 ,  H01L43/02 ,  H01L27/22

Abstract: The present invention provides a magnetoresistance effect element with a high read operation speed, a magnetic memory array, a magnetic memory device, and a write method for a magnetoresistance effect element. A magnetoresistance effect element includes: a heavy metal layer; a magnetic recording unit including a recording layer that includes a ferromagnetic layer that is magnetized in a vertical direction with respect to a film surface and is provided on a front surface of the heavy metal layer, a barrier layer that is provided on a surface of the recording layer which is opposite to the heavy metal layer and is formed from an insulator, and a reference layer which is provided on a surface of the barrier layer which is opposite to the recording layer, and a magnetization of the reference layer is fixed in the vertical direction with respect to a film surface; an insulating layer that is provided on a surface of the heavy metal layer which is opposite to the magnetic recording unit; a first terminal that is connected to the insulating layer at a position facing the recording layer with the heavy metal layer and the insulating layer interposed therebetween and applies a voltage to the heavy metal layer through the insulating layer; a second terminal that is connected to the reference layer; and a third terminal and a fourth terminal which are connected to the heavy metal layer, and cause a write current to flow to the heavy metal layer between the magnetic recording unit and the insulating layer.

公开(公告)号：US20210125654A1

公开(公告)日：2021-04-29

申请号：US17254592

申请日：2019-06-20

Applicant: TOHOKU UNIVERSITY

Inventor： Tetsuo Endoh ,  Yoshiaki Saito ,  Shoji Ikeda

IPC: G11C11/16

Abstract: A magnetic memory device includes: a memory cell array including a plurality of lines arranged parallel to one another at predetermined intervals and extending in one direction, and a plurality of memory cells connected to the plurality of lines and arranged in a matrix along an extending direction of the plurality of lines and along an arrangement direction of the plurality of lines, each of the plurality of memory cells including a magnetoresistance effect element; a selection circuit connected to the plurality of lines and configured to select non-adjacent lines that are not adjacent to one another, from the plurality of lines; and a controller connected to the selection circuit and configured to cause the selection circuit to select the non-adjacent lines and allow a write current to flow through the non-adjacent lines simultaneously in writing data on the memory cell array.

公开(公告)号：US20210119114A1

公开(公告)日：2021-04-22

申请号：US16967364

申请日：2019-01-30

Applicant: TOHOKU UNIVERSITY

Inventor： Shunsuke Fukami ,  Aleksandr Kurenkov ,  William Andrew Borders ,  Hideo Ohno ,  Tetsuo Endoh

IPC: H01L43/04 ,  H01L27/22 ,  H01L43/06 ,  H01L43/10 ,  G11C11/16 ,  G11C11/18 ,  G11C11/54 ,  G06N3/063

Abstract: There is provided a magnetoresistance effect element includes: a channel layer that extends in a first direction; a recording layer which includes a film formed from a ferromagnetic material, of which a magnetization state is changed to one of two or greater magnetization states, and which is formed on the channel layer; a non-magnetic layer that is provided on a surface of the recording layer; a reference layer which is provided on a surface of the non-magnetic layer, which includes a film formed from a ferromagnetic material, and of which a magnetization direction is fixed; a terminal pair that includes a first terminal and a second terminal which are electrically connected to the channel layer with an interval in the first direction, and to which a current pulse for bringing the recording layer to any one magnetization state with a plurality of pulses is input by flowing a current to the channel layer between the first terminal and the second terminal; and a third terminal that is electrically connected to the reference layer.

公开(公告)号：US20210110857A1

公开(公告)日：2021-04-15

申请号：US17043257

申请日：2019-03-12

Applicant: TOHOKU UNIVERSITY

Inventor： Tetsuo Endoh ,  Shoji Ikeda ,  Hiroki Koike

IPC: G11C11/16 ,  H01L43/02 ,  G11C13/00

Abstract: An integrated circuit device of the invention, includes: a first resistance variable memory element provided on a semiconductor substrate; a second resistance variable memory element provided on the semiconductor substrate; and a semiconductor circuit for controlling write and read of the first resistance variable memory element and the second resistance variable memory element, which is provided on the semiconductor substrate, in which the second resistance variable memory element has a write current that is smaller than a write current of the first resistance variable memory element, and the second resistance variable memory element is disposed farther from the semiconductor substrate than the first resistance variable memory element.

公开(公告)号：US10896729B2

公开(公告)日：2021-01-19

申请号：US16463938

申请日：2017-10-31

Applicant: Tohoku University

Inventor： Takahiro Hanyu ,  Daisuke Suzuki ,  Hideo Ohno ,  Tetsuo Endoh

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/15 ,  G11C11/16

Abstract: A data write circuit of a resistive memory element is provided, the device being capable of writing with low writing energy using a simple circuit. The data write circuit of the resistive memory element, includes: a complementary resistive memory element; writing means for making the complementary resistive memory element cause a resistance change; detection means for detecting a writing state in the complementary resistive memory element; and control means for controlling writing by the writing means, based on a detected signal of the detection means.

公开(公告)号：US10833256B2

公开(公告)日：2020-11-10

申请号：US16328852

申请日：2017-03-21

Applicant: TOHOKU UNIVERSITY

Inventor： Hiroaki Honjo ,  Tetsuo Endoh ,  Shoji Ikeda ,  Hideo Sato ,  Hideo Ohno

IPC: H01L43/12 ,  H01L43/10 ,  H01L43/08 ,  H01L43/02 ,  H01L27/22

Abstract: A magnetic tunnel junction element includes, in a following stack order, an underlayer formed of a metal material, a fixed layer formed of a ferromagnetic body, a magnetic coupling layer formed of a nonmagnetic body, a reference layer formed of a ferromagnetic body, a barrier layer formed of a nonmagnetic body, and a recording layer formed of a ferromagnetic body, or alternatively, the magnetic tunnel junction element includes, in a following stack order, a recording layer formed of a ferromagnetic body, a barrier layer formed of a nonmagnetic body, a reference layer formed of a ferromagnetic body, a magnetic coupling layer formed of a nonmagnetic body, an underlayer formed of a metal material, and a fixed layer formed of a ferromagnetic body, wherein the fixed layer is formed and stacked after performing plasma treatment to a surface of the underlayer having been formed.

公开(公告)号：US10410703B2

公开(公告)日：2019-09-10

申请号：US15810896

申请日：2017-11-13

Applicant: TOHOKU UNIVERSITY

Inventor： Shunsuke Fukami ,  Toru Iwabuchi ,  Hideo Ohno ,  Tetsuo Endoh

IPC: G11C11/00 ,  G11C11/02 ,  H01L43/08 ,  G01R33/09 ,  G11C7/10 ,  G11C11/16 ,  H01F1/00 ,  H01F10/32 ,  B82Y10/00 ,  B82Y25/00

Abstract: A magnetoresistance effect element includes a recording layer containing a ferromagnetic body, and including a first fixed and second magnetization regions having magnetization components fixed substantially in a direction antiparallel to the in-plane direction to each other, and a free magnetization region disposed between the first and second fixed magnetization regions and having a magnetization component invertible in the in-plane direction, a domain wall disposed between the first fixed magnetization region and the free magnetization region, and being movable within the free magnetization region, and a magnetic nanowire having a width of 40 nm or less. The thickness of the recording layer is 40 nm or less and at least half but no more than twofold the width of the magnetic nanowire. The element further includes a barrier layer disposed on the recording layer, and a reference layer disposed on the barrier layer and containing a ferromagnetic body.

公开(公告)号：US20190019944A1

公开(公告)日：2019-01-17

申请号：US15776902

申请日：2016-11-18

Applicant: TOHOKU UNIVERSITY

Inventor： Hideo Sato ,  Yoshihisa Horikawa ,  Shunsuke Fukami ,  Shoji Ikeda ,  Fumihiro Matsukura ,  Hideo Ohno ,  Tetsuo Endoh ,  Hiroaki Honjo

IPC: H01L43/08 ,  H01L43/10 ,  H01L43/02 ,  G11C11/16

Abstract: A magnetic tunnel junction element (10) includes a configuration in which a reference layer (14) that includes a ferromagnetic material, a barrier layer (15) that includes O, a recording layer (16) that includes a ferromagnetic material including Co or Fe, a first protective layer (17) that includes O, and a second protective layer (18) that includes at least one of Pt, Ru, Co, Fe, CoB, FeB, or CoFeB are layered.