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    Semiconductor device
    71.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11817503B2

    公开(公告)日：2023-11-14

    申请号：US17875152

    申请日：2022-07-27

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Che-Cheng Chang ,  Chih-Han Lin

    IPC: H01L29/00 ,  H01L29/78 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

    CPC classification number: H01L29/7851 ,  H01L29/42356 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

    Abstract: A device includes a substrate, a shallow trench isolation (STI) structure, an isolation structure, and a gate stack. The substrate has a semiconductor fin. The shallow trench isolation (STI) structure is over the substrate and laterally surrounding the semiconductor fin. The isolation structure is disposed on a top surface of the STI structure. The gate stack crosses the semiconductor fin, over the STI structure, and in contact with a sidewall the isolation structure, in which the gate stack includes a high-k dielectric layer extending from a sidewall of the semiconductor fin to the top surface of the STI structure and terminating prior to reaching the sidewall of the isolation structure, and the high-k dielectric layer is in contact with the top surface of the STI structure. The gate stack includes a gate electrode over the high-k dielectric layer and in contact with the sidewall of the isolation structure.

    Selective Removal of Gate Dielectric from Dummy Fin
    76.
    发明申请
    Selective Removal of Gate Dielectric from Dummy Fin 有权

    公开(公告)号：US20220359721A1

    公开(公告)日：2022-11-10

    申请号：US17814756

    申请日：2022-07-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shih-Yao Lin ,  Chih-Han Lin

    IPC: H01L29/66 ,  H01L29/51 ,  H01L29/78 ,  H01L21/8234

    Abstract: A method includes forming an active channel region, forming a dummy channel region, forming a first gate dielectric layer over the active channel region, forming a second gate dielectric layer over the dummy channel region, removing the second gate dielectric layer from the dummy channel region, forming a gate isolation region over and contacting the dummy channel region, and forming a first gate stack and a second gate stack. The first gate stack is on the active channel region. The gate isolation region separates the first gate stack from the second gate stack.

    Methods for forming stacked layers and devices formed thereof
    77.
    发明授权
    Methods for forming stacked layers and devices formed thereof 有权

    公开(公告)号：US11488858B2

    公开(公告)日：2022-11-01

    申请号：US16870389

    申请日：2020-05-08

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shih-Yao Lin ,  Kuei-Yu Kao ,  Chen-Ping Chen ,  Chih-Han Lin

    IPC: H01L21/768 ,  H01L21/3065 ,  H01L21/306

    Abstract: A method includes etching a semiconductor substrate to form a trench, with the semiconductor substrate having a sidewall facing the trench, and depositing a first semiconductor layer extending into the trench. The first semiconductor layer includes a first bottom portion at a bottom of the trench, and a first sidewall portion on the sidewall of the semiconductor substrate. The first sidewall portion is removed to reveal the sidewall of the semiconductor substrate. The method further includes depositing a second semiconductor layer extending into the trench, with the second semiconductor layer having a second bottom portion over the first bottom portion, and a second sidewall portion contacting the sidewall of the semiconductor substrate. The second sidewall portion is removed to reveal the sidewall of the semiconductor substrate.

    Transistor gates and methods of forming thereof
    78.
    发明授权
    Transistor gates and methods of forming thereof 有权

    公开(公告)号：US11437287B2

    公开(公告)日：2022-09-06

    申请号：US16871514

    申请日：2020-05-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shih-Yao Lin ,  Chih-Han Lin ,  Shu-Uei Jang ,  Ya-Yi Tsai ,  Shu-Yuan Ku

    IPC: H01L21/8238 ,  H01L21/28 ,  H01L27/092 ,  H01L29/49 ,  H01L29/66

    Abstract: A device includes a semiconductor substrate and a first gate stack over the semiconductor substrate, the first gate stack being between a first gate spacer and a second gate spacer. The device further includes a second gate stack over the semiconductor substrate between the first gate spacer and the second gate spacer and a dielectric material separating the first gate stack from the second gate stack. The dielectric material is at least partially between the first gate spacer and the second gate spacer, a first width of an upper portion of the dielectric material is greater than a second width of a lower portion of the dielectric material, and a third width of an upper portion of the first gate spacer is less than a fourth width of a lower portion of the first gate spacer.

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