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    WELL PICK-UP REGION DESIGN FOR IMPROVING MEMORY MACRO PERFORMANCE
    71.
    发明公开
    WELL PICK-UP REGION DESIGN FOR IMPROVING MEMORY MACRO PERFORMANCE 审中-公开

    公开(公告)号：US20240237323A1

    公开(公告)日：2024-07-11

    申请号：US18444889

    申请日：2024-02-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Chuan Yang ,  Chang-Ta Yang ,  Ping-Wei Wang

    IPC: H10B10/00 ,  G06F30/30 ,  G11C11/412

    CPC classification number: H10B10/00 ,  G06F30/30 ,  G11C11/412

    Abstract: Well pick-up (WPU) regions are disclosed herein for improving performance of memory arrays, such as static random access memory arrays. An exemplary semiconductor device includes a circuit region, a first WPU region, second WPU region, a first well of a first conductivity type, and a second well of a second conductivity type. The circuit region, the first WPU region, and the second WPU region are arranged along a first direction in sequence. The first well has a first portion disposed in the circuit region and a second portion disposed in the first WPU region. The second well has a first portion disposed in the circuit region, a second portion disposed in the first WPU region, and a third potion disposed in the second WPU region. Measured along the first direction a width of the first WPU region is less than a width of the second WPU region.

    FINFET CIRCUIT DEVICES WITH WELL ISOLATION
    72.
    发明公开
    FINFET CIRCUIT DEVICES WITH WELL ISOLATION 审中-公开

    公开(公告)号：US20240222188A1

    公开(公告)日：2024-07-04

    申请号：US18609639

    申请日：2024-03-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Chuan Yang ,  Chang-Ta Yang

    IPC: H01L21/762 ,  H01L21/3065 ,  H10B10/00

    CPC classification number: H01L21/76224 ,  H01L21/3065 ,  H01L21/76232 ,  H10B10/12

    Abstract: A method includes receiving a structure that includes a substrate including a first well region having a first dopant type and a second well region having a second dopant type that is opposite to the first dopant type; and fins extending above the substrate. The method further includes forming a patterned etch mask on the structure, wherein the patterned etch mask provides an opening that is directly above a first fin of the fins, wherein the first fin is directly above the first well region. The method further includes etching the structure through the patterned etch mask, wherein the etching removes the first fin and forms a recess in the substrate that spans from the first well region into the second well region; and forming a dielectric material between remaining portions of the fins and within the recess.

    Memory device and method for forming the same
    76.
    发明授权
    Memory device and method for forming the same 有权

    公开(公告)号：US11563013B2

    公开(公告)日：2023-01-24

    申请号：US17035371

    申请日：2020-09-28

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Hsin-Wen Su ,  Chih-Chuan Yang ,  Shih-Hao Lin ,  Yu-Kuan Lin ,  Lien-Jung Hung ,  Ping-Wei Wang

    IPC: H01L21/8234 ,  H01L21/768 ,  H01L27/11 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66

    Abstract: A memory device includes a substrate, first semiconductor fin, second semiconductor fin, first gate structure, second gate structure, first gate spacer, and a second gate spacer. The first gate structure crosses the first semiconductor fin. The second gate structure crosses the second semiconductor fin, the first gate structure extending continuously from the second gate structure, in which in a top view of the memory device, a width of the first gate structure is greater than a width of the second gate structure. The first gate spacer is on a sidewall of the first gate structure. The second gate spacer extends continuously from the first gate spacer and on a sidewall of the second gate structure, in which in the top view of the memory device, a width of the first gate spacer is less than a width of the second gate spacer.

    Integrated chip with improved latch-up immunity
    78.
    发明授权
    Integrated chip with improved latch-up immunity 有权

    公开(公告)号：US11257817B2

    公开(公告)日：2022-02-22

    申请号：US16808866

    申请日：2020-03-04

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsin-Wen Su ,  Lien Jung Hung ,  Ping-Wei Wang ,  Wen-Chun Keng ,  Chih-Chuan Yang ,  Shih-Hao Lin

    IPC: H01L27/092 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  H01L21/8238

    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC) having a device section and a pick-up section. The IC includes a semiconductor substrate. A first fin of the semiconductor substrate is disposed in the device section. A second fin of the semiconductor substrate is disposed in the pick-up section and laterally spaced from the first fin in a first direction. A gate structure is disposed in the device section and laterally spaced from the second fin in the first direction. The gate structure extends laterally over the semiconductor substrate and the first fin in a second direction perpendicular to the first direction. A pick-up region is disposed on the second fin. The pick-up region continuously extends from a first sidewall of the second fin to a second sidewall of the second fin. The first sidewall is laterally spaced from the second sidewall in the first direction.

    INTEGRATED CHIP WITH IMPROVED LATCH-UP IMMUNITY
    80.
    发明申请
    INTEGRATED CHIP WITH IMPROVED LATCH-UP IMMUNITY 有权

    公开(公告)号：US20210280584A1

    公开(公告)日：2021-09-09

    申请号：US16808866

    申请日：2020-03-04

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsin-Wen Su ,  Lien Jung Hung ,  Ping-Wei Wang ,  Wen-Chun Keng ,  Chih-Chuan Yang ,  Shih-Hao Lin

    IPC: H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L21/8238

    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC) having a device section and a pick-up section. The IC includes a semiconductor substrate. A first fin of the semiconductor substrate is disposed in the device section. A second fin of the semiconductor substrate is disposed in the pick-up section and laterally spaced from the first fin in a first direction. A gate structure is disposed in the device section and laterally spaced from the second fin in the first direction. The gate structure extends laterally over the semiconductor substrate and the first fin in a second direction perpendicular to the first direction. A pick-up region is disposed on the second fin. The pick-up region continuously extends from a first sidewall of the second fin to a second sidewall of the second fin. The first sidewall is laterally spaced from the second sidewall in the first direction.

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