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    FIN ISOLATION STRUCTURES OF SEMICONDUCTOR DEVICES
    74.
    发明申请
    FIN ISOLATION STRUCTURES OF SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20190096768A1

    公开(公告)日：2019-03-28

    申请号：US15718752

    申请日：2017-09-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kuo-Cheng Ching ,  Chih-Hao Wang ,  Kuan-Lun Cheng ,  Yen-Ming Chen

    IPC: H01L21/8234 ,  H01L21/762 ,  H01L21/02

    Abstract: A method of forming a fin field effect transistor (finFET) on a substrate includes forming a fin structure on the substrate and forming a shallow trench isolation (STI) region on the substrate. First and second fin portions of the fin structure extend above a top surface of the STI region. The method further includes oxidizing the first fin portion to convert a first material of the first fin portion to a second material. The second material is different from the first material of the first fin portion and a material of the second fin portion. The method further includes forming an oxide layer on the oxidized first fin portion and the second fin portion and forming first and second polysilicon structures on the oxide layer.

    BACKSIDE PN JUNCTION DIODE
    75.
    发明申请
    BACKSIDE PN JUNCTION DIODE 有权

    公开(公告)号：US20250142950A1

    公开(公告)日：2025-05-01

    申请号：US19004755

    申请日：2024-12-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Xuan Huang ,  Ching-Wei Tsai ,  Jam-Wem Lee ,  Kuo-Ji Chen ,  Kuan-Lun Cheng

    IPC: H10D84/83 ,  H10D30/01 ,  H10D30/62 ,  H10D62/10 ,  H10D84/80

    Abstract: The present disclosure provides embodiments of semiconductor devices. A semiconductor device according to the present disclosure include an elongated semiconductor member surrounded by an isolation feature and extending lengthwise along a first direction, a first source/drain feature and a second source/drain feature over a top surface of the elongated semiconductor member, a vertical stack of channel members each extending lengthwise between the first source/drain feature and the second source/drain feature along the first direction, a gate structure wrapping around each of the channel members, an epitaxial layer deposited on the bottom surface of the elongated semiconductor member, a silicide layer disposed on the epitaxial layer, and a conductive layer disposed on the silicide layer.

    Packaged semiconductor devices including backside power rails and methods of forming the same
    78.
    发明授权
    Packaged semiconductor devices including backside power rails and methods of forming the same 有权

    公开(公告)号：US12166016B2

    公开(公告)日：2024-12-10

    申请号：US18446626

    申请日：2023-08-09

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chi-Yi Chuang ,  Hou-Yu Chen ,  Kuan-Lun Cheng

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/528 ,  H01L25/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786

    Abstract: Methods for forming packaged semiconductor devices including backside power rails and packaged semiconductor devices formed by the same are disclosed. In an embodiment, a device includes a first integrated circuit device including a first transistor structure in a first device layer; a front-side interconnect structure on a front-side of the first device layer; and a backside interconnect structure on a backside of the first device layer, the backside interconnect structure including a first dielectric layer on the backside of the first device layer; and a first contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and a second integrated circuit device including a second transistor structure in a second device layer; and a first interconnect structure on the second device layer, the first interconnect structure being bonded to the front-side interconnect structure by dielectric-to-dielectric and metal-to-metal bonds.

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