公开(公告)号：US11508692B2

公开(公告)日：2022-11-22

申请号：US16888868

申请日：2020-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kung-Chen Yeh ,  Szu-Wei Lu ,  Tsung-Fu Tsai ,  Ying-Ching Shih

IPC: H01L21/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L21/304 ,  H01L21/56 ,  H01L21/78 ,  H01L21/268

Abstract: A package structure including an interposer, at least one semiconductor die and an insulating encapsulation is provided. The interposer includes a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, the interconnect structure includes interlayer dielectric films and interconnect wirings embedded in the interlayer dielectric films, the semiconductor substrate includes a first portion and a second portion disposed on the first portion, the first interconnect structure is disposed on the second portion, and a first maximum lateral dimension of the first portion is greater than a second maximum lateral dimension of the second portion. The at least one semiconductor die is disposed over and electrically connected to the interconnect structure. The insulating encapsulation is disposed on the first portion, wherein the insulating encapsulation laterally encapsulates the least one semiconductor die and the second portion.

公开(公告)号：US11502056B2

公开(公告)日：2022-11-15

申请号：US16924147

申请日：2020-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Yu Huang ,  Chih-Wei Wu ,  Sung-Hui Huang ,  Shang-Yun Hou ,  Ying-Ching Shih ,  Cheng-Chieh Li

IPC: H01L23/48 ,  H01L23/00

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes first and second package components stacked upon and electrically connected to each other. The first package component includes first and second conductive bumps, the second package component includes third and fourth conductive bumps, and dimensions of the first and second conductive bumps are less than those of the third and fourth conductive bumps. The semiconductor package includes a first joint structure partially wrapping the first conductive bump and the third conductive bump, and a second joint structure partially wrapping the second conductive bump and the fourth conductive bump. A curvature of the first joint structure is different from a curvature of the second joint structure.

公开(公告)号：US11424194B2

公开(公告)日：2022-08-23

申请号：US16595741

申请日：2019-10-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Wu ,  Ying-Ching Shih ,  Szu-Wei Lu ,  Jing-Cheng Lin

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/14 ,  H01L23/48 ,  H01L23/498 ,  H01L23/31

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure has a first conductive layer on a first substrate and a second conductive layer on a second substrate. A bonding structure is disposed between the first conductive layer and the second conductive layer. A support structure is disposed between the first substrate and the second substrate. A passivation layer covers a bottom surface of the first conductive layer and has a lower surface facing an uppermost surface of the support structure.

公开(公告)号：US11424173B2

公开(公告)日：2022-08-23

申请号：US17068064

申请日：2020-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chih-Wei Wu ,  Ying-Ching Shih ,  Szu-Wei Lu

IPC: H01L23/31 ,  H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L23/18 ,  H01L21/822 ,  H01L25/11

Abstract: An integrated circuit package and a method of forming the same are provided. A method includes stacking a plurality of integrated circuit dies on a wafer to form a die stack. A bonding process is performed on the die stack. The bonding process mechanically and electrically connects adjacent integrated circuit dies of the die stack to each other. A dam structure is formed over the wafer. The dam structure surrounds the die stack. A first encapsulant is formed over the wafer and between the die stack and the dam structure. The first encapsulant fills gaps between the adjacent integrated circuit dies of the die stack. A second encapsulant is formed over the wafer. The second encapsulant surrounds the die stack, the first encapsulant and the dam structure.

公开(公告)号：US11183482B2

公开(公告)日：2021-11-23

申请号：US16572628

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Wu ,  Ying-Ching Shih ,  Hsien-Ju Tsou

IPC: H01L21/56 ,  H01L21/78 ,  H01L21/66 ,  H01L23/00 ,  H01L23/544

Abstract: A shift control method in manufacture of semiconductor device includes at least the following step. An overlay offset of a first target of a semiconductor die and a second target of the semiconductor die is determined, where the second target is disposed on the first target. The semiconductor die is placed over a carrier, where placing the semiconductor die includes feeding back the overlay offset to result in a positional control of the semiconductor die. The semiconductor die is post processed to form a semiconductor device. Other shift control methods in manufacture of semiconductor device are also provided.

公开(公告)号：US11133289B2

公开(公告)日：2021-09-28

申请号：US16414723

申请日：2019-05-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Fu Tsai ,  Shih-Ting Lin ,  Szu-Wei Lu ,  Ying-Ching Shih

IPC: H01L25/04 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L21/683 ,  H01L21/78

Abstract: A semiconductor package includes a first integrated circuit structure, a second integrated circuit structure, a plurality of conductive bumps, an encapsulating material, and a redistribution structure. The first integrated circuit structure includes an active surface having a plurality of contact pads, a back surface opposite to the active surface, and a plurality of through vias extending through the first integrated circuit structure and connecting the active surface and the back surface. The second integrated circuit structure is disposed on the back surface of the first integrated circuit structure. The conductive bumps are disposed between the first integrated circuit structure and the second integrated circuit structure, and electrically connecting the plurality of through vias and the second integrated circuit structure. The encapsulating material at least encapsulates the second integrated circuit structure. The redistribution structure is disposed over and electrically connected to the active surface of the first integrated circuit structure.

公开(公告)号：US11088086B2

公开(公告)日：2021-08-10

申请号：US16395385

申请日：2019-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun-Ting Chen ,  Ying-Ching Shih ,  Szu-Wei Lu ,  Chih-Wei Wu

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L21/56 ,  H01L23/31

Abstract: A method for forming a chip package structure is provided. The method includes bonding a first chip structure and a second chip structure to a surface of a substrate. The first chip structure and the second chip structure are spaced apart from each other. There is a first gap between the first chip structure and the second chip structure. The method includes removing a first portion of the first chip structure and a second portion of the second chip structure to form a trench partially in the first chip structure and the second chip structure and partially over the first gap. The method includes forming an anti-warpage bar in the trench. The anti-warpage bar is over the first chip structure, the second chip structure, and the first gap.

公开(公告)号：US20210066211A1

公开(公告)日：2021-03-04

申请号：US16865432

申请日：2020-05-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Fu Tsai ,  Kung-Chen Yeh ,  Li-Chung Kuo ,  Szu-Wei Lu ,  Ying-Ching Shih

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

Abstract: A package structure includes a circuit substrate and a semiconductor package. The semiconductor package is disposed on the circuit substrate, and includes a plurality of semiconductor dies, an insulating encapsulant and a connection structure. The insulating encapsulant comprises a first portion and a second portion protruding from the first portion, the first portion is encapsulating the plurality of semiconductor dies and has a planar first surface, and the second portion has a planar second surface located at a different level than the planar first surface. The connection structure is located over the first portion of the insulating encapsulant on the planar first surface, and located on the plurality of semiconductor dies, wherein the connection structure is electrically connected to the plurality of semiconductor dies and the circuit substrate.

公开(公告)号：US20200176384A1

公开(公告)日：2020-06-04

申请号：US16655260

申请日：2019-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Wu ,  Chen-Hua Yu ,  Kuo-Chung Yee ,  Szu-Wei Lu ,  Ying-Ching Shih

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48

Abstract: Provided are a package and a method of manufacturing the same. The package includes a first die, a second die, a bridge structure, an encapsulant, and a redistribution layer (RDL) structure. The first die and the second die are disposed side by side. The bridge structure is disposed over the first die and the second die to electrically connect the first die and the second die. The encapsulant laterally encapsulates the first die, the second die, and the bridge structure. The RDL structure is disposed over a backside of the bridge structure and the encapsulant. The RDL structure includes an insulating structure and a conductive pattern, the conductive pattern is disposed over the insulating structure and extending through the insulating structure and a substrate of the bridge structure, so as to form at least one through via in the substrate of the bridge structure.

公开(公告)号：US20200075546A1

公开(公告)日：2020-03-05

申请号：US16116892

申请日：2018-08-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Ching Shih ,  Chih-Wei Wu ,  Szu-Wei Lu

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L21/56

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first chip, a second chip, self-aligned structures, a bridge structure, and an insulating encapsulant. The first chip has a first rear surface opposite to a first active surface. The second chip is disposed beside the first chip and has a second rear surface opposite to a second active surface. The self-aligned structures are disposed on the first rear surface of the first chip and the second rear surface of the second chip. The bridge structure is electrically connected to the first chip and the second chip. The insulating encapsulant covers at least the side surfaces of the first and second chips, a side surface of the semiconductor substrate, and the side surfaces of the self-aligned structures.