公开(公告)号：US20170140945A1

公开(公告)日：2017-05-18

申请号：US15418949

申请日：2017-01-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L21/48 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L23/373

Abstract: A method of forming a semiconductor package includes providing a substrate, wherein the substrate has at least one chip attached on an upper surface of the substrate. An insulating barrier layer is deposited above the substrate, wherein the at least one chip is at least partially embedded within the insulating barrier layer. A thermally conductive layer is formed over the insulating barrier layer to at least partially encapsulate the at least one chip.

公开(公告)号：US20250167075A1

公开(公告)日：2025-05-22

申请号：US18512194

申请日：2023-11-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Jen Lien ,  Chen-Hua Yu ,  Cheng-Chieh Hsieh ,  Kuo-Chung Yee ,  Hung-Yi Kuo ,  Ke-Han Shen

IPC: H01L23/473 ,  H01L21/48 ,  H01L23/00 ,  H01L23/48

Abstract: Semiconductor devices and methods of manufacture are presented herein. In accordance with some embodiments, a device includes a first semiconductor device, the first semiconductor device including a first interconnect structure, an integrated cooling structure bonded to the first interconnect structure, wherein the integrated cooling structure is configured for a working fluid to enter and exit the integrated cooling structure, a second semiconductor device including a second interconnect structure, the second semiconductor device bonded to the integrated cooling structure opposite the first interconnect structure, and a plurality of through substrate vias extending through the integrated cooling structure, wherein the plurality of through substrate vias electrically couple the first semiconductor device to the second semiconductor device.

公开(公告)号：US20250164690A1

公开(公告)日：2025-05-22

申请号：US18593331

申请日：2024-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Lin ,  Yu-Hao Kuo ,  Chih-Hao Yu ,  Ren-Fen Tsui ,  Jui Lin Chao ,  Hsing-Kuo Hsia ,  Kuo-Chung Yee ,  Chen-Hua Yu

IPC: G02B6/122 ,  G02B6/12 ,  G02B6/13

Abstract: Optical devices and methods of manufacture are presented in which metallization layers are formed over a first active layer of first optical components, a first opening is formed through the metallization layers, a first semiconductor die is bonded over the metallization layers, and a laser die is bonded over the metallization layers, wherein after the bonding the laser die a first mirror located within the laser die is aligned with a second mirror through the first opening.

公开(公告)号：US12300646B2

公开(公告)日：2025-05-13

申请号：US18517774

申请日：2023-11-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee

IPC: H01L23/00 ,  H01L23/48

Abstract: A method includes forming integrated circuits on a front side of a first chip, performing a backside grinding on the first chip to reveal a plurality of through-vias in the first chip, and forming a first bridge structure on a backside of the first chip using a damascene process. The bridge structure has a first bond pad, a second bond pad, and a conductive trace electrically connecting the first bond pad to the second bond pad. The method further includes bonding a second chip and a third chip to the first chip through face-to-back bonding. A third bond pad of the second chip is bonded to the first bond pad of the first chip. A fourth bond pad of the third chip is bonded to the second bond pad of the first chip.

公开(公告)号：US12272613B2

公开(公告)日：2025-04-08

申请号：US17861556

申请日：2022-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ming Wang ,  Yu-Hung Lin ,  Shih-Peng Tai ,  Kuo-Chung Yee

IPC: H01L29/15 ,  H01L23/00 ,  H01L23/367 ,  H01L23/48 ,  H01L25/065 ,  H01L31/0312

Abstract: A semiconductor device includes an integrated circuit structure and a thermal pillar over the integrated circuit structure. The integrated circuit structure includes a semiconductor substrate including circuitry, a dielectric layer over the semiconductor substrate, an interconnect structure over the dielectric layer, and a first thermal fin extending through the semiconductor substrate, the dielectric layer, and the interconnect structure. The first thermal fin is electrically isolated from the circuitry. The thermal pillar is thermally coupled to the first thermal fin.

公开(公告)号：US12218089B2

公开(公告)日：2025-02-04

申请号：US18153847

申请日：2023-01-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee ,  Chih-Hang Tung

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: A semiconductor device includes a first die, a second die on the first die, and a third die on the second die, the second die being interposed between the first die and the third die. The first die includes a first substrate and a first interconnect structure on an active side of the first substrate. The second die includes a second substrate, a second interconnect structure on a backside of the second substrate, and a power distribution network (PDN) structure on the second interconnect structure such that the second interconnect structure is interposed between the PDN structure and the second substrate.

公开(公告)号：US12209015B2

公开(公告)日：2025-01-28

申请号：US18316391

申请日：2023-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee

IPC: B81B7/00 ,  B81C1/00

Abstract: Microelectromechanical systems (MEMS) packages and methods of manufacture thereof are described. In an embodiment, a method of manufacturing a MEMS package may include attaching a MEMS structure having a capping structure thereon to a device wafer comprising a plurality of first devices formed therein to form a wafer level MEMS package; and singulating the device wafer having the MEMS structure attached thereto to form a plurality of chip scale MEMS packages.

公开(公告)号：US11685648B2

公开(公告)日：2023-06-27

申请号：US17379119

申请日：2021-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00238 ,  B81B7/0006 ,  B81C1/00269 ,  B81C2203/0118 ,  B81C2203/0792 ,  H01L2224/48091 ,  H01L2924/16235 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: Microelectromechanical systems (MEMS) packages and methods of manufacture thereof are described. In an embodiment, a method of manufacturing a MEMS package may include attaching a MEMS structure having a capping structure thereon to a device wafer comprising a plurality of first devices formed therein to form a wafer level MEMS package; and singulating the device wafer having the MEMS structure attached thereto to form a plurality of chip scale MEMS packages.

公开(公告)号：US20230123427A1

公开(公告)日：2023-04-20

申请号：US18068010

申请日：2022-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee ,  Hao-Yi Tsai ,  Tin-Hao Kuo

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/538 ,  H01L21/48

Abstract: A method includes forming a through-via from a first conductive pad of a first device die. The first conductive pad is at a top surface of the first device die. A second device die is adhered to the top surface of the first device die. The second device die has a surface conductive feature. The second device die and the through-via are encapsulated in an encapsulating material. The encapsulating material is planarized to reveal the through-via and the surface conductive feature. Redistribution lines are formed over and electrically coupled to the through-via and the surface conductive feature.

公开(公告)号：US11574853B2

公开(公告)日：2023-02-07

申请号：US16916115

申请日：2020-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chun-Hui Yu ,  Jeng-Nan Hung ,  Kuo-Chung Yee ,  Po-Fan Lin

IPC: H01L23/46 ,  H01L23/367 ,  H01L23/433 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor device including a substrate, a semiconductor package, a thermal conductive bonding layer, and a lid is provided. The semiconductor package is disposed on the substrate. The thermal conductive bonding layer is disposed on the semiconductor package. The lid is attached to the thermal conductive bonding layer and covers the semiconductor package to prevent coolant from contacting the semiconductor package.