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公开(公告)号：US20210313292A1
公开(公告)日：2021-10-07
申请号：US16836934
申请日：2020-04-01
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Po-Han Wang , Hung-Jui Kuo , Shih-Peng Tai , Yu-Hsiang Hu , I-Chia Chen
IPC: H01L23/00
Abstract: A semiconductor package including a plurality of semiconductor devices, an insulating layer, and a redistribution layer is provided. The insulating layer is disposed over the semiconductor device. The redistribution layer is disposed over the insulating layer and electrically connected to the semiconductor device. The redistribution layer includes a conductive line portion. The semiconductor package has a stitching zone, and the insulating layer has a ridge structure on a surface away from the semiconductor device and positioned within the stitching zone.
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公开(公告)号：US20240319590A1
公开(公告)日：2024-09-26
申请号：US18186413
申请日：2023-03-20
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Hung Lin , Yu-Yi Huang , Chih-Hao Yu , Yu-Ting Yen , Shih-Peng Tai
CPC classification number: G03F7/0005 , G03F7/0757 , G03F7/091 , G03F7/167 , G03F7/7015
Abstract: Optical devices and methods of manufacture are presented in which a first mask is utilized for multiple purposes. Some methods include depositing a first mask over a support material, forming a concave surface in the support material through the first mask, and bonding the first mask to a first bonding layer over an optical interposer.
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公开(公告)号：US20240153901A1
公开(公告)日：2024-05-09
申请号：US18151714
申请日：2023-01-09
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Hung Lin , Han-Jong Chia , Wei-Ming Wang , Kuo-Chung Yee , Chen Chen , Shih-Peng Tai
IPC: H01L23/00
CPC classification number: H01L24/08 , H01L24/05 , H01L24/80 , H01L24/13 , H01L2224/05553 , H01L2224/05555 , H01L2224/05556 , H01L2224/05571 , H01L2224/05624 , H01L2224/05647 , H01L2224/05649 , H01L2224/05657 , H01L2224/05666 , H01L2224/0568 , H01L2224/05684 , H01L2224/0603 , H01L2224/06181 , H01L2224/06505 , H01L2224/08123 , H01L2224/08147 , H01L2224/13147 , H01L2224/80357 , H01L2224/80379 , H01L2224/80896 , H01L2924/04642 , H01L2924/0544 , H01L2924/059
Abstract: A first and second semiconductor device are bonded together using a bonding contact pad embedded within a bonding dielectric layer of the first semiconductor device and at least one bonding via embedded within a bonding dielectric layer of the second semiconductor device. The bonding contact pad extends a first dimension in a first direction perpendicular to the major surface of the first semiconductor device and a second dimension in a second direction parallel to the plane of the first semiconductor wafer, the second dimension being at least twice the first dimension. The bonding via extends a third dimension in the first direction and a fourth dimension in the second direction, the third dimension being at least twice the first dimension. The bonding contact pad and bonding via may be at least partially embedded in respective bonding dielectric layers in respective topmost dielectric layers of respective stacked interconnect layers.
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公开(公告)号：US20240047216A1
公开(公告)日：2024-02-08
申请号：US17816782
申请日：2022-08-02
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Wei-Ming Wang , Yu-Hung Lin , Shih-Peng Tai , Kuo-Chung Yee
IPC: H01L21/308 , H01L21/311 , H01L23/00
CPC classification number: H01L21/308 , H01L21/31144 , H01L24/80 , H01L2224/80895 , H01L2224/80896
Abstract: A method includes forming an etching mask over a first wafer. The etching mask covers an inner portion of the first wafer. A wafer edge trimming process is performed to trim an edge portion of the first wafer, with the etching mask protecting the inner portion of the first wafer from being etched. The edge portion forms a full ring encircling the inner portion of the first wafer. The method further includes removing the etching mask, and bonding the first wafer to a second wafer.
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公开(公告)号：US20240014091A1
公开(公告)日：2024-01-11
申请号：US17861556
申请日：2022-07-11
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
Inventor： Wei-Ming Wang , Yu-Hung Lin , Shih-Peng Tai , Kuo-Chung Yee
IPC: H01L23/367 , H01L23/00 , H01L23/48 , H01L25/065
CPC classification number: H01L23/367 , H01L24/08 , H01L23/481 , H01L25/0657 , H01L24/05 , H01L2224/05624 , H01L2224/05647 , H01L2224/08145 , H01L2224/08245 , H01L2224/06181 , H01L2224/0557 , H01L2224/80896 , H01L24/80 , H01L24/32 , H01L2224/32245 , H01L2224/2929 , H01L2224/29393 , H01L2224/29193 , H01L24/29 , H01L23/3675 , H01L2225/06589
Abstract: A semiconductor device includes an integrated circuit structure and a thermal pillar over the integrated circuit structure. The integrated circuit structure includes a semiconductor substrate including circuitry, a dielectric layer over the semiconductor substrate, an interconnect structure over the dielectric layer, and a first thermal fin extending through the semiconductor substrate, the dielectric layer, and the interconnect structure. The first thermal fin is electrically isolated from the circuitry. The thermal pillar is thermally coupled to the first thermal fin.
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公开(公告)号：US11682647B2
公开(公告)日：2023-06-20
申请号：US16836934
申请日：2020-04-01
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Po-Han Wang , Hung-Jui Kuo , Shih-Peng Tai , Yu-Hsiang Hu , I-Chia Chen
IPC: H01L23/00
CPC classification number: H01L24/20 , H01L24/19 , H01L2224/2101 , H01L2224/2105
Abstract: A semiconductor package including a plurality of semiconductor devices, an insulating layer, and a redistribution layer is provided. The insulating layer is disposed over the semiconductor device. The redistribution layer is disposed over the insulating layer and electrically connected to the semiconductor device. The redistribution layer includes a conductive line portion. The semiconductor package has a stitching zone, and the insulating layer has a ridge structure on a surface away from the semiconductor device and positioned within the stitching zone.
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公开(公告)号：US20210098330A1
公开(公告)日：2021-04-01
申请号：US16805869
申请日：2020-03-02
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shih-Hui Wang , Der-Chyang Yeh , Shih-Peng Tai , Tsung-Shu Lin , Yi-Chung Huang
IPC: H01L23/367 , H01L23/00 , H01L23/13 , H01L23/498
Abstract: A package structure including a substrate, a semiconductor device, a heat spreader, and an adhesive layer is provided. The semiconductor device is bonded onto the substrate, wherein an angle θ is formed between one sidewall of the semiconductor device and one sidewall of the substrate, 0°
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公开(公告)号：US20240103218A1
公开(公告)日：2024-03-28
申请号：US18153661
申请日：2023-01-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hsing-Kuo Hsia , Jui Lin Chao , Chen-Hua Yu , Chih-Hao Yu , Shih-Peng Tai
CPC classification number: G02B6/122 , G02B6/13 , G02B2006/12121
Abstract: Optical devices and methods of manufacture are presented in which a laser die or other heterogeneous device is embedded within an optical device and evanescently coupled to other devices. The evanescent coupling can be performed either from the laser die to a waveguide, to an external cavity, to an external coupler, or to an interposer substrate.
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公开(公告)号：US20170345741A1
公开(公告)日：2017-11-30
申请号：US15201604
申请日：2016-07-04
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chi-Hsi Wu , Chun-Yi Liu , Der-Chyang Yeh , Hsien-Wei Chen , Shih-Peng Tai , Chuen-De Wang
IPC: H01L23/495 , H01L21/56 , H01L23/31 , H01L25/065 , H01L21/48
CPC classification number: H01L23/49527 , H01L21/4821 , H01L21/4825 , H01L21/565 , H01L21/568 , H01L23/3114 , H01L23/3178 , H01L23/4952 , H01L23/49589 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/97 , H01L25/0655 , H01L2224/04105 , H01L2224/12105 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2924/1431 , H01L2924/1434 , H01L2924/18162 , H01L2924/19011
Abstract: An integrated fan-out package is described. The integrated fan-out package comprises a first die and a second die arranged adjacent to each other. A molding compound encapsulates the first and second dies. A redistribution structure is disposed over the molding compound and on the first and second dies. The redistribution structure comprises a first connection structure electrically connected to the first die, a second connection structure electrically connected to the second die and an inter-dielectric layer located between the first and second connection structures and separating the first connection structure from the second connection structure. The ball pad is disposed on the redistribution structure and electrically connected with the first die or the second die. The bridge structure is disposed on the first connection structure and on the second connection structure and electrically connects the first die with the second die.
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公开(公告)号：US20250031434A1
公开(公告)日：2025-01-23
申请号：US18353389
申请日：2023-07-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Hung Lin , Jih-Churng Twu , Su-Chun Yang , Shih-Peng Tai , Yu-Hao Kuo
IPC: H01L21/822 , H01L21/3065 , H01L21/311 , H01L21/56 , H01L23/00 , H01L23/31 , H01L23/498 , H01L25/065
Abstract: A method includes bonding a first semiconductor die and a second semiconductor die to a substrate, where a gap is disposed between a first sidewall of the first semiconductor die and a second sidewall of the second semiconductor die, performing a plasma treatment to dope top surfaces and sidewalls of each of the first semiconductor die and the second semiconductor die with a first dopant, where a concentration of the first dopant in the first sidewall decreases in a vertical direction from a top surface of the first semiconductor die towards a bottom surface of the first semiconductor die, and a concentration of the first dopant in the second sidewall decreases in a vertical direction from a top surface of the second semiconductor die towards a bottom surface of the second semiconductor die, and filling the gap with a spin-on dielectric material.
