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公开(公告)号：US06260107B1
公开(公告)日：2001-07-10
申请号：US09520726
申请日：2000-03-08
申请人： Kunio Uchiyama , Osamu Nishii
发明人： Kunio Uchiyama , Osamu Nishii
IPC分类号： G06F1202
CPC分类号： G11C8/18 , G11C7/1006 , G11C7/1072 , G11C8/12 , H04N19/423 , H04N19/61
摘要： A main storage apparatus is a synchronous dynamic memory having a plurality of memory banks and a mode register for determining an operation mode, a main storage controller is coupled to a processor and the main storage apparatus, and means to realize controlling of parallel access to a plurality of banks of the memory and controlling of setting of an operation mode to the built-in register is arranged in the main storage controller. Accordingly, the use of a conventional processor of high generality and a conventional memory can be ensured.
摘要翻译： 主存储装置是具有多个存储体的同步动态存储器和用于确定操作模式的模式寄存器，主存储控制器耦合到处理器和主存储装置，以及用于实现对并行访问的控制的装置 在主存储控制器中布置有多个存储器组以及将操作模式设置到内置寄存器的控制。 因此，可以确保使用高通用性和常规存储器的常规处理器。
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公开(公告)号：US5860000A
公开(公告)日：1999-01-12
申请号：US594763
申请日：1996-01-31
CPC分类号： G06F9/3885 , G06F9/30149 , G06F9/3861
摘要： An FPU pipeline is synchronized with a CPU pipeline. Synchronization is achieved by having stalls and freezes in any one pipeline cause stalls and freezes in the other pipeline as well. Exceptions are kept precise even for long floating point operations. Precise exceptions are achieved by having a first execution stage of the FPU pipeline generate a busy signal, when a first floating point instruction enters a first execution stage of the FPU pipeline. When a second floating point instruction is decoded by the FPU pipeline before the first floating point instruction has finished executing in the first stage of the FPU pipeline, then both pipelines are stalled.
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公开(公告)号：US5809274A
公开(公告)日：1998-09-15
申请号：US886464
申请日：1997-07-01
IPC分类号： G06F9/30 , G06F9/312 , G06F9/34 , G06F9/345 , G06F9/38 , G06F9/445 , G06F12/00 , G06F12/02 , G06F12/08 , G06F12/10 , G06F12/12 , G06F13/16 , G06F15/78
CPC分类号： G06F9/30047 , G06F12/0848 , G06F12/0891 , G06F9/30043 , G06F9/3802 , G06F9/3824
摘要： A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory. The data processor also includes an instruction controller reading out an instruction from the first associative memory when the instructioon is present in the first associative memory and reading an instruction from the main memory when the instruction is not present in the first associative memory. The controller also has as an output the instruction to be executed. An instruction execution unit has a second associative memory storing operand data read out from the main memory. An instruction executioner executes the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.
摘要翻译： 用于使用存储在主存储器中的操作数数据执行指令的数据处理器包括指令控制单元，其具有存储从主存储器读出的指令的第一关联存储器。 当指令存在于第一关联存储器中时，数据处理器还包括从第一关联存储器读取指令的指令控制器，并且当指令不存在于第一关联存储器中时，从主存储器读取指令。 控制器还具有要执行的指令作为输出。 指令执行单元具有存储从主存储器读出的操作数数据的第二关联存储器。 当操作数数据存在于第二关联存储器中时，当操作数数据不存在于第二关联存储器中时，指令执行器通过使用从第二关联存储器读出的操作数数据执行指令。
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74.发明授权Data processor with on-chip cache memory and purge controller responsive to external signal for controlling access to the cache memory 失效具有片上高速缓冲存储器和清除控制器的数据处理器，响应于外部信号，用于控制对高速缓冲存储器的访问
公开(公告)号：US5680631A
公开(公告)日：1997-10-21
申请号：US978069
申请日：1992-11-18
IPC分类号： G06F9/30 , G06F9/312 , G06F9/34 , G06F9/345 , G06F9/38 , G06F9/445 , G06F12/00 , G06F12/02 , G06F12/08 , G06F12/10 , G06F12/12 , G06F13/16 , G06F15/78
CPC分类号： G06F9/30047 , G06F12/0848 , G06F12/0891 , G06F9/30043 , G06F9/3802 , G06F9/3824
摘要： A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory. The data processor also includes an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and reading an instruction from the main memory when the instruction is not present in the first associative memory. The controller also has as an output; and an instruction execution unit has a second associative memory storing operand data read out from the main memory. An instruction executioner executes the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.
摘要翻译： 用于使用存储在主存储器中的操作数数据执行指令的数据处理器包括指令控制单元，其具有存储从主存储器读出的指令的第一关联存储器。 当指令存在于第一关联存储器中时，数据处理器还包括从第一关联存储器读取指令的指令控制器，并且当指令不存在于第一关联存储器中时，从主存储器读取指令。 控制器也有输出; 并且指令执行单元具有存储从主存储器读出的操作数数据的第二关联存储器。 当操作数数据存在于第二关联存储器中时，当操作数数据不存在于第二关联存储器中时，指令执行器通过使用从第二关联存储器读出的操作数数据执行指令。
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75.发明授权Branching system for return from subroutine using target address in return buffer accessed based on branch type information in BHT 失效基于BHT中的分支类型信息访问的返回缓冲区的子程序返回的分支系统
公开(公告)号：US5454087A
公开(公告)日：1995-09-26
申请号：US965441
申请日：1992-10-23
申请人： Susumu Narita , Fumio Arakawa , Kunio Uchiyama , Hirokazu Aoki
发明人： Susumu Narita , Fumio Arakawa , Kunio Uchiyama , Hirokazu Aoki
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/4426
摘要： An address of a branch instruction, a branch target address thereof, and a type thereof are stored as branch history information in a branch instruction buffer. In addition, a return address for a return from a subroutine is retained in a return buffer. A look-up operation is conducted through the buffer by using the pre-fetch address such that when a hit occurs, a branch target address is output from the buffer depending on a branch instruction type. Consequently, the branch processing is achieved at a high speed. Particularly, the processing speed of an unconditional branch instruction containing a return instruction is increased.
摘要翻译： 分支指令的地址，分支目标地址及其类型作为分支历史信息存储在分支指令缓冲器中。 另外，从子程序返回的返回地址保留在返回缓冲区中。 通过使用预取地址来进行通过缓冲器的查找操作，使得当命中发生时，根据分支指令类型从缓冲器输出分支目标地址。 因此，以高速实现分支处理。 特别地，包含返回指令的无条件转移指令的处理速度增加。
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76.发明授权Data processor having two instruction registers connected in cascade and two instruction decoders 失效数据处理器具有串联连接的两个指令寄存器和两个指令解码器
公开(公告)号：US5301285A
公开(公告)日：1994-04-05
申请号：US940762
申请日：1992-09-04
申请人： Makoto Hanawa , Osamu Nishii , Susumu Narita , Kunio Uchiyama
发明人： Makoto Hanawa , Osamu Nishii , Susumu Narita , Kunio Uchiyama
CPC分类号： G06F9/3822
摘要： A data processor is provided with a first register storing a first half word of one instruction; a second register storing a second half word of the instruction; a first decoder decoding the first half word and at the same time detecting whether there exists an addressing extension portion between the first half word and the second half word; a second decoder decoding the second half word; and, a decode result generating circuit, to which a detection signal of the first decoder indicates whether the addressing extension portion exists. A decode result of the first decoder and a decode result of the second decoder are supplied to the decode result generating circuit. An extension portion register is provided to store the addressing extension portion. When the first decoder detects the addressing extension portion, the decode result generating circuit invalidates the decode result of the second decoder. On the other hand, in the case where there exists no addressing extension portion, the decode result generating circuit judges, on the basis of the detection signal, that the decode result of the second decoder is valid.
摘要翻译： 数据处理器设置有存储一个指令的前半字的第一寄存器; 存储指令的第二个半字的第二寄存器; 解码所述前半字，并且同时检测在所述前半字和所述第二半字之间是否存在寻址扩展部分的第一解码器; 解码所述第二半字的第二解码器; 以及第一解码器的检测信号指示寻址扩展部分是否存在的解码结果生成电路。 第一解码器的解码结果和第二解码器的解码结果被提供给解码结果生成电路。 提供扩展部分寄存器以存储寻址扩展部分。 当第一解码器检测到寻址扩展部分时，解码结果生成电路使第二解码器的解码结果无效。 另一方面，在不存在寻址扩展部的情况下，解码结果生成电路根据检测信号判断第二解码器的解码结果有效。
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77.发明授权Multiprocessor cache system having three states for generating invalidating signals upon write accesses 失效具有三种状态的多处理器缓存系统，用于在写访问时产生无效信号
公开(公告)号：US5283886A
公开(公告)日：1994-02-01
申请号：US950746
申请日：1992-09-24
申请人： Osamu Nishii , Kunio Uchiyama , Hirokazu Aoki , Kanji Oishi , Jun Kitano , Susumu Hatano
发明人： Osamu Nishii , Kunio Uchiyama , Hirokazu Aoki , Kanji Oishi , Jun Kitano , Susumu Hatano
CPC分类号： G06F12/0833
摘要： Herein disclosed is a multiprocessor system which comprises first and second processors (1001 and 1002), first and second cache memories (100:#1 and #2), an address bus (123), a data bus (126), an invalidating signal line (PURGE:131) and a main memory (1004). The first and second cache memories are operated by the copy-back method. The state of the data of the first cache (100:#1) exists in one state selected from a group consisting of an invalid first state, a valid and non-updated second state and a valid and updated third state. The second cache (100:#2) is constructed like the first cache. When the write access of the first processor hits the first cache, the state of the data of the first cache is shifted from the second state to the third state, and the first cache outputs the address of the write hit and the invalidating signal to the address bus and the invalidating signal line, respectively. When the write access from the first processor misses the first cache, a data of one block is block-transferred from the main memory to the first cache, and the invalidating signal is outputted. After this, the first cache executes the write of the data in the transfer block. In case the first and second caches hold the data in the third state relating to the pertinent address when an address of an access request is fed to the address bus (123), the pertinent cache writes back the pertinent data in the main memory.
摘要翻译： 这里公开了一种多处理器系统，其包括第一和第二处理器（1001和1002），第一和第二高速缓冲存储器（100：＃1和＃2），地址总线（123），数据总线（126），无效信号 线（PURGE：131）和主存储器（1004）。 第一和第二高速缓存存储器通过复制方法操作。 第一高速缓存（100：＃1）的数据的状态存在于从由无效的第一状态，有效和未更新的第二状态以及有效和更新的第三状态组成的组中选择的一个状态中。 第二个缓存（100：＃2）被构造成像第一个缓存。 当第一处理器的写入访问第一高速缓存时，第一高速缓存的数据的状态从第二状态转移到第三状态，并且第一高速缓存将写入命中的地址和无效信号输出到 地址总线和无效信号线。 当来自第一处理器的写访问错过第一高速缓存时，一个块的数据被从主存储器块传输到第一高速缓存，并且输出无效信号。 之后，第一个缓存执行传输块中数据的写入。 在第一和第二高速缓冲存储器将存取请求地址与相关地址相关的第三状态的数据保存到地址总线（123）的情况下，相关高速缓冲存储器将相关数据写回到主存储器中。
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78.发明授权Single-chip pipeline processor for fetching/flushing instruction/data caches in response to first/second hit/mishit signal respectively detected in corresponding to their logical addresses 失效单芯片流水线处理器，用于根据其逻辑地址分别检测到的第一/第二命中/虚拟信号来提取/刷新指令/数据高速缓存
公开(公告)号：US5206945A
公开(公告)日：1993-04-27
申请号：US606804
申请日：1990-10-31
CPC分类号： G06F9/3802 , G06F12/0848 , G06F12/0891 , G06F9/30047 , G06F9/3824
摘要： A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory, and an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and from the main memory when the instruction is not present in the first associative memory the instruction control unit produces an output to be executed. An instruction execution unit has a second associative memory that stores operand data read out from the main memory, and an instruction executioner executing the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.
摘要翻译： 用于使用存储在主存储器中的操作数数据执行指令的数据处理器包括指令控制单元，该指令控制单元具有存储从主存储器读出的指令的第一关联存储器，以及指令控制单元，当指令为指令时，从第一关联存储器读出指令 存在于第一关联存储器中，并且当指令不存在于第一关联存储器中时，指令控制单元产生要执行的输出。 指令执行单元具有第二关联存储器，其存储从主存储器读出的操作数数据，以及指令执行器，当所述操作数数据存在于所述第二关联存储器中时，通过使用从所述第二关联存储器读出的操作数据来执行所述指令; 当操作数数据不存在于第二关联存储器中时，从主存储器。
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79.发明授权Data processor with on-chip logical addressing and off-chip physical addressing 失效具有片上逻辑寻址和片外物理寻址的数据处理器
公开(公告)号：US5129075A
公开(公告)日：1992-07-07
申请号：US596751
申请日：1990-10-12
IPC分类号： G06F9/30 , G06F9/312 , G06F9/34 , G06F9/345 , G06F9/38 , G06F9/445 , G06F12/00 , G06F12/02 , G06F12/08 , G06F12/10 , G06F12/12 , G06F13/16 , G06F15/78
CPC分类号： G06F9/30047 , G06F12/0848 , G06F12/0891 , G06F9/30043 , G06F9/3802 , G06F9/3824
摘要： A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory, and the instruction control unit also includes an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and from the main memory when the instruction is not present in the first associative memory. The instruction controller provides the instruction to be executed as an output. The data processor further includes an instruction execution unit having a second associative memory storing operand data read out from the main memory, and an instruction execution unit that executes the instruction. The instruction execution unit uses operand data read out from the second associative memory when the operand data is present in the second associative memory and operand data from the main memory when the operand data is not present in the second associative memory.
摘要翻译： 用于使用存储在主存储器中的操作数数据执行指令的数据处理器包括指令控制单元，其具有存储从主存储器读出的指令的第一关联存储器，并且指令控制单元还包括指令控制器，其从第一 当指令存在于第一关联存储器中时，并且当指令不存在于第一关联存储器中时，与主存储器相关联的存储器。 指令控制器提供要作为输出执行的指令。 数据处理器还包括具有存储从主存储器读出的操作数数据的第二关联存储器的指令执行单元和执行该指令的指令执行单元。 当操作数数据存在于第二关联存储器中时，指令执行单元使用从第二关联存储器读出的操作数数据，当操作数数据不存在于第二关联存储器中时，来自主存储器的操作数数据。
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