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公开(公告)号：US12102014B2
公开(公告)日：2024-09-24
申请号：US18376437
申请日：2023-10-03
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chia-Chang Hsu , Chen-Yi Weng , Chin-Yang Hsieh , Jing-Yin Jhang
CPC classification number: H10N50/80 , G11C11/161 , H01F10/3254 , H01F41/34 , H10B61/00 , H10N50/01 , H10N50/85
Abstract: A semiconductor device includes a substrate comprising a MTJ region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region, and a contact plug on the logic region. Preferably, the MTJ includes a bottom electrode layer having a gradient concentration, a free layer on the bottom electrode layer, and a top electrode layer on the free layer.
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公开(公告)号：US20240306514A1
公开(公告)日：2024-09-12
申请号：US18126486
申请日：2023-03-27
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Che-Wei Chang , Ching-Hua Hsu , Chen-Yi Weng , Po-Kai Hsu
IPC: H10N50/10 , H01L23/522 , H01L23/528 , H10B61/00 , H10N50/80
CPC classification number: H10N50/10 , H01L23/5226 , H01L23/5283 , H10B61/00 , H10N50/80
Abstract: A magnetic random access memory structure includes a first dielectric layer; a bottom electrode layer disposed on the first dielectric layer; a spin orbit coupling layer disposed on the bottom electrode layer; a magnetic tunneling junction (MTJ) element disposed on the spin orbit coupling layer; a top electrode layer disposed on the MTJ element; a protective layer surrounding the MTJ element and the top electrode layer, and the protective layer masking the spin orbit coupling layer; and a spacer layer surrounding the protective layer.
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公开(公告)号：US12029139B2
公开(公告)日：2024-07-02
申请号：US18202275
申请日：2023-05-25
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Yu-Ping Wang , Chen-Yi Weng , Chin-Yang Hsieh , Si-Han Tsai , Che-Wei Chang , Jing-Yin Jhang
Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.
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公开(公告)号：US11957064B2
公开(公告)日：2024-04-09
申请号：US17967904
申请日：2022-10-18
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chen-Yi Weng , Yi-Wei Tseng , Chin-Yang Hsieh , Jing-Yin Jhang , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , I-Ming Tseng , Yu-Ping Wang
CPC classification number: H10N50/80 , G11C5/06 , G11C11/16 , G11C11/161 , H01L29/82 , H10N50/01 , H10N50/10 , G11C2211/5615 , H10B61/00
Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.
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公开(公告)号：US20240081157A1
公开(公告)日：2024-03-07
申请号：US18502103
申请日：2023-11-06
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chen-Yi Weng , Yi-Wei Tseng , Chin-Yang Hsieh , Jing-Yin Jhang , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , I-Ming Tseng , Yu-Ping Wang
CPC classification number: H10N50/80 , G11C5/06 , G11C11/16 , G11C11/161 , H01L29/82 , H10N50/01 , H10N50/10 , G11C2211/5615 , H10B61/00
Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.
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Patent Agency Ranking
公开(公告)号：US20240027549A1
公开(公告)日：2024-01-25
申请号：US18376451
申请日：2023-10-04
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chen-Yi Weng , Che-Wei Chang , Si-Han Tsai , Ching-Hua Hsu , Jing-Yin Jhang , Yu-Ping Wang
CPC classification number: G01R33/093 , G01R33/098 , G11C11/02 , H10B61/00 , H10N50/01 , H10N50/10 , H10N50/80 , H10N50/85
Abstract: A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, a top electrode is formed on the MTJ stack, the top electrode, the free layer, and the barrier layer are removed, a first cap layer is formed on the top electrode, the free layer, and the barrier layer, and the first cap layer and the pinned layer are removed to form a MTJ and a spacer adjacent to the MTJ.
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公开(公告)号：US20230403946A1
公开(公告)日：2023-12-14
申请号：US18239079
申请日：2023-08-28
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Tai-Cheng Hou , Wei-Xin Gao , Fu-Yu Tsai , Chin-Yang Hsieh , Chen-Yi Weng , Jing-Yin Jhang , Bin-Siang Tsai , Kun-Ju Li , Chih-Yueh Li , Chia-Lin Lu , Chun-Lung Chen , Kun-Yuan Laio , Yu-Tsung Lai , Wei-Hao Huang
IPC: H10N50/10 , H01L21/768 , H01L21/762 , H10N50/80
CPC classification number: H10N50/10 , H01L21/76802 , H01L21/762 , H10N50/80 , H10N35/01
Abstract: A method for fabricating semiconductor device includes first forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, performing an atomic layer deposition (ALD) process or a high-density plasma (HDP) process to form a passivation layer on the first MTJ and the second MTJ, performing an etching process to remove the passivation layer adjacent to the first MTJ and the second MTJ, and then forming an ultra low-k (ULK) dielectric layer on the passivation layer.
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公开(公告)号：US11821964B2
公开(公告)日：2023-11-21
申请号：US16927918
申请日：2020-07-13
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chen-Yi Weng , Che-Wei Chang , Si-Han Tsai , Ching-Hua Hsu , Jing-Yin Jhang , Yu-Ping Wang
CPC classification number: G01R33/093 , G01R33/098 , G11C11/02 , H10B61/00 , H10N50/01 , H10N50/10 , H10N50/80 , H10N50/85
Abstract: A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, a top electrode is formed on the MTJ stack, the top electrode, the free layer, and the barrier layer are removed, a first cap layer is formed on the top electrode, the free layer, and the barrier layer, and the first cap layer and the pinned layer are removed to form a MTJ and a spacer adjacent to the MTJ.
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公开(公告)号：US11818965B2
公开(公告)日：2023-11-14
申请号：US17867702
申请日：2022-07-19
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chia-Chang Hsu , Chen-Yi Weng , Chin-Yang Hsieh , Jing-Yin Jhang
CPC classification number: H10N50/80 , G11C11/161 , H01F10/3254 , H01F41/34 , H10B61/00 , H10N50/01 , H10N50/85
Abstract: A semiconductor device includes a substrate comprising a MTJ region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region, and a contact plug on the logic region. Preferably, the MTJ includes a bottom electrode layer having a gradient concentration, a free layer on the bottom electrode layer, and a top electrode layer on the free layer.
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公开(公告)号：US11706996B2
公开(公告)日：2023-07-18
申请号：US17463541
申请日：2021-08-31
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Yu-Ping Wang , Chen-Yi Weng , Chin-Yang Hsieh , Si-Han Tsai , Che-Wei Chang , Jing-Yin Jhang
Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.
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