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    Liquid crystal display device
    71.
    发明授权
    Liquid crystal display device 有权
    液晶显示装置

    公开(公告)号：US07522143B2

    公开(公告)日：2009-04-21

    申请号：US11326694

    申请日：2006-01-06

    申请人： Chul-Woo Park ,  Tae-Soo Kim

    发明人： Chul-Woo Park ,  Tae-Soo Kim

    IPC分类号： G09G3/36

    CPC分类号： G09G3/3648 ,  G09G3/3685 ,  G09G3/3696 ,  G09G2300/0491 ,  G09G2310/027 ,  G09G2320/0252

    摘要： The present invention relates to a liquid crystal display device with a source driver in which a signal without a significant delay is generated, which has a fast response speed and provides a liquid crystal display device having a scan driver comprising a memory in which gradation data values are stored in a lookup table and which sequentially outputs a plurality of switching signals corresponding to the gradation data inputted The device also includes a switching part to which the plurality of switching signals are applied to sequentially select a plurality of voltage levels so that a plurality of pulse waveforms corresponding to the selected plurality of voltage levels are sequentially applied to the respective pixels including liquid crystal cells during one frame, wherein the liquid crystal display further includes a voltage generation part for producing the plurality of voltage levels, the memory outputs a switching signal for resetting the liquid crystal cells in the early stage of each frame, and the liquid crystal cells are OCB liquid crystal cells.

    摘要翻译： 本发明涉及具有源驱动器的液晶显示装置，其中产生没有显着延迟的信号，其具有快速的响应速度并提供具有扫描驱动器的液晶显示装置，该扫描驱动器包括存储器，其中灰度数据值 存储在查找表中，并且顺序地输出与输入的灰度数据相对应的多个切换信号。该设备还包括切换部分，多个切换信号被施加到该切换部分以顺序地选择多个电压电平，使得多个 对应于所选择的多个电压电平的脉冲波形在一帧期间依次施加到包括液晶单元的各个像素，其中液晶显示器还包括用于产生多个电压电平的电压产生部分，存储器输出切换信号 用于在早期阶段复位液晶单元 ，液晶单元为OCB液晶单元。

    Semiconductor memory device and arrangement method thereof
    73.
    发明授权
    Semiconductor memory device and arrangement method thereof 失效
    半导体存储器件及其布置方法

    公开(公告)号：US07391636B2

    公开(公告)日：2008-06-24

    申请号：US11863151

    申请日：2007-09-27

    申请人： Chul-Woo Park ,  Sung-Hoon Kim ,  Hyuk-Joon Kwon ,  Jung-Bae Lee ,  Youn-Sik Park

    发明人： Chul-Woo Park ,  Sung-Hoon Kim ,  Hyuk-Joon Kwon ,  Jung-Bae Lee ,  Youn-Sik Park

    IPC分类号： G11C5/06

    CPC分类号： H01L27/0207 ,  G11C5/025 ,  G11C5/063 ,  G11C7/18 ,  H01L23/5226 ,  H01L27/0203 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor memory device and an arrangement method thereof are included. The semiconductor memory device includes column selecting signal lines and global data IO signal lines arranged on the same layer in the same direction above a memory cell array; word lines and first local data IO signal lines arranged on a different layer from the column selecting signal lines above the memory cell array, in a perpendicular direction to the column selecting signal lines; and second local data IO signal lines arranged on a different layer from the column selecting signal lines and the word lines above the memory cell array, in the same direction as the first local data IO signal lines.

    摘要翻译： 包括半导体存储器件及其布置方法。 半导体存储器件包括在存储单元阵列上方沿相同方向布置在同一层上的列选择信号线和全局数据IO信号线; 在与列选择信号线垂直的方向上与位于存储单元阵列上方的列选择信号线布置在不同层上的字线和第一本地数据IO信号线; 以及在与第一本地数据IO信号线相同的方向上与列选择信号线和存储单元阵列上方的字线​​布置在不同层上的第二本地数据IO信号线。

    Semiconductor memory device
    74.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US07342837B2

    公开(公告)日：2008-03-11

    申请号：US11435636

    申请日：2006-05-17

    申请人： Chul-Woo Park

    发明人： Chul-Woo Park

    IPC分类号： G11C7/00

    CPC分类号： G11C11/4074 ,  G11C5/14 ,  G11C7/1045 ,  G11C2207/105

    摘要： A semiconductor memory device includes a semiconductor chip including a first voltage generating circuit that generates a first voltage in response to a first operation control signal, a second voltage generating circuit that generates a second voltage in response to a second operation control signal, a first operation control circuit that generates the first operation control signal, a second operation control circuit that generates the second operation control signal, a first bonding pad connected to an output of the first voltage generating circuit, and a second bonding pad connected to an output of the second voltage generating circuit. A packaging substrate includes a first substrate pad connected to the first bonding pad and a second substrate pad connected to the second bonding pad. The first and second substrate pads are connected to each other through the packaging substrate.

    摘要翻译： 半导体存储器件包括：半导体芯片，包括响应于第一操作控制信号产生第一电压的第一电压产生电路;响应于第二操作控制信号产生第二电压的第二电压产生电路;第一操作 产生第一操作控制信号的控制电路，产生第二操作控制信号的第二操作控制电路，连接到第一电压产生电路的输出的第一焊盘和连接到第二操作控制信号的输出的第二焊盘 电压发生电路。 封装衬底包括连接到第一焊盘的第一衬底焊盘和连接到第二焊盘的第二衬底焊盘。 第一和第二基板焊盘通过封装基板相互连接。

    Semiconductor memory devices and signal line arrangements and related methods
    76.
    发明申请
    Semiconductor memory devices and signal line arrangements and related methods 失效
    半导体存储器件和信号线布置及相关方法

    公开(公告)号：US20060056218A1

    公开(公告)日：2006-03-16

    申请号：US11221684

    申请日：2005-09-08

    申请人： Chul-Woo Park ,  Jung-Bae Lee ,  Young-Sun Min ,  Jong-Hyun Choi ,  Jong-Eon Lee

    发明人： Chul-Woo Park ,  Jung-Bae Lee ,  Young-Sun Min ,  Jong-Hyun Choi ,  Jong-Eon Lee

    IPC分类号： G11C5/06

    CPC分类号： G11C5/063 ,  G11C7/18 ,  G11C8/14

    摘要： A semiconductor memory device may include a memory cell array, a bit line sense amplifier, a sub word line driver, and an electrode. The memory cell array may include a sub memory cell array connected between sub word lines and bit line pairs and having memory cells which are selected in response to a signal transmitted to the sub word lines and column selecting signal lines. The bit line sense amplifier may be configures to sense and amplify data of the bit line pairs. The sub word line driver may be configured to combine signals transmitted from word selecting signal lines and signals transmitted from main word lines to select the sub word lines. Moreover, the memory cell array may be configured to transmit data between the bit line pairs and local data line pairs and to transmit data between the local data line pairs and global data line pairs. The electrode may be configured to cover the whole memory cell array and to apply a voltage needed for the memory cells. The local data line pairs may be arranged on a first layer above the electrode in the same direction as the sub word line. The column selecting signal lines and the global data line pairs may be arranged on a second layer above the electrode in the same direction as the bit line. The word selecting signal lines and the main word lines may be arranged on a third layer above the electrode in the same direction as the sub word line. Related methods of signal line arrangement are also discussed.

    摘要翻译： 半导体存储器件可以包括存储单元阵列，位线读出放大器，子字线驱动器和电极。 存储单元阵列可以包括连接在子字线和位线对之间并具有响应于发送到子字线和列选择信号线的信号而被选择的存储器单元的子存储单元阵列。 位线读出放大器可以被配置为感测和放大位线对的数据。 子字线驱动器可以被配置为组合从字选择信号线发送的信号和从主字线发送的信号，以选择子字线。 此外，存储单元阵列可以被配置为在位线对和本地数据线对之间传输数据，并且在本地数据线对和全局数据线对之间传送数据。 电极可以被配置为覆盖整个存储单元阵列并施加存储单元所需的电压。 局部数据线对可以以与子字线相同的方向布置在电极上方的第一层上。 列选择信号线和全局数据线对可以以与位线相同的方向布置在电极上方的第二层上。 字选择信号线和主字线可以沿着与子字线相同的方向布置在电极上方的第三层上。 还讨论了信号线布置的相关方法。

    Semiconductor memory device and arrangement method thereof
    77.
    发明申请
    Semiconductor memory device and arrangement method thereof 失效
    半导体存储器件及其布置方法

    公开(公告)号：US20060055045A1

    公开(公告)日：2006-03-16

    申请号：US11225221

    申请日：2005-09-12

    申请人： Chul-Woo Park ,  Sung-Hoon Kim ,  Hyuk-Joon Kwon ,  Jung-Bae Lee ,  Youn-Sik Park

    发明人： Chul-Woo Park ,  Sung-Hoon Kim ,  Hyuk-Joon Kwon ,  Jung-Bae Lee ,  Youn-Sik Park

    IPC分类号： H01L29/40

    CPC分类号： H01L27/0207 ,  G11C5/025 ,  G11C5/063 ,  G11C7/18 ,  H01L23/5226 ,  H01L27/0203 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor memory device and an arrangement method thereof are disclosed. The semiconductor memory device comprises column selecting signal lines and global data IO signal lines arranged on the same layer in the same direction above a memory cell array; word lines and first local data IO signal lines arranged on a different layer from the column selecting signal lines above the memory cell array, in a perpendicular direction to the column selecting signal lines; and second local data IO signal lines arranged on a different layer from the column selecting signal lines and the word lines above the memory cell array, in the same direction as the first local data IO signal lines.

    摘要翻译： 公开了一种半导体存储器件及其布置方法。 半导体存储器件包括在存储单元阵列上方沿相同方向布置在同一层上的列选择信号线和全局数据IO信号线; 在与列选择信号线垂直的方向上与位于存储单元阵列上方的列选择信号线布置在不同层上的字线和第一本地数据IO信号线; 以及在与第一本地数据IO信号线相同的方向上与列选择信号线和存储单元阵列上方的字线​​布置在不同层上的第二本地数据IO信号线。