公开(公告)号：US5247644A

公开(公告)日：1993-09-21

申请号：US651128

申请日：1991-02-06

申请人： William M. Johnson ,  David B. Witt

发明人： William M. Johnson ,  David B. Witt

IPC分类号： G06F12/06

CPC分类号： G06F12/0607

摘要： A processing system provides efficient accessing by a processor of a memory during a sequential memory access. The processing system includes a memory having a plurality of storage locations, each being addressable at a corresponding different storage address, a processor coupled to the memory for addressing the memory storage locations for accessing the storage locations and control means coupled to the memory and to the processor. The control means is responsive to a sequential access by the processor for causing the processor to address selected spaced apart ones of the storage locations in order and is arranged to access the other memory locations in order between the processor addresses to provide an access rate of one word of information per system clock cycle.

公开(公告)号：US5210841A

公开(公告)日：1993-05-11

申请号：US472099

申请日：1990-01-30

申请人： William M. Johnson

发明人： William M. Johnson

IPC分类号： G06F9/355 ,  G06F9/38 ,  G06F12/10

CPC分类号： G06F12/1027

摘要： A new and improved external memory accessing system for use in a microprocessor. The system includes a physical address cache for storing a plurality of entries including register numbers and corresponding translated external memory address locations which were used for execution of previous load instructions. The system further includes means responsive to a current load instruction for determining if the address of the register specified in the load instruction is within the physical address cache and means for conveying to the external memory, at the beginning of the execution stage of the load instruction, a previously translated external memory physical address corresponding to a specified register stored in the physical address cache. Also disclosed is a new and improved address generator for generating a new translated external memory physical address which is conveyed to the external memory and to the physical address cache for updating the physical address cache.

公开(公告)号：US5185878A

公开(公告)日：1993-02-09

申请号：US626239

申请日：1990-12-12

申请人： Gigy Baror ,  William M. Johnson

发明人： Gigy Baror ,  William M. Johnson

IPC分类号： G06F12/08

CPC分类号： G06F12/0848

摘要： Methods and apparatus are disclosed for realizing an integrated cache unit (ICU) comprising both a cache memory and a cache controller on a single chip. The novel ICU is capable of being programmed, supports high speed data and instruction processing applications in both Reduced Instruction Set Computers (RISC) and non-RISC architecture environments, and supports high speed processing applications in both single and multiprocessor systems. The preferred ICU has two buses, one for the processor interface and the other for a memory interface. The ICU support single, burst and pipelined processor accesses and is capable of operating at frequencies in excess of 25 megahertz, achieving processor access times of two cycles for the first access in a sequence, and one cycle for burst mode or piplined accesses. It can be used as either an instruction or data cache with flexible internal cache organization. A RISC processor and two ICUs (for instruction and data cache) implements a very high performance processor with 16k bytes of cache. Larger caches can be designed by using additional ICUs which, according to the preferred embodiment of the invention, are modular. Further features include flexible and extensive multiprocessor support hardware, low power requirements, and support of a combination of bus watching, ownership schemes, software control and hardware control schemes which may be used with the novel ICU to achieve cache consistency.

摘要翻译： 公开了用于在单个芯片上实现包括高速缓冲存储器和高速缓存控制器的集成缓存单元（ICU）的方法和装置。 新型ICU能够被编程，支持精简指令集计算机（RISC）和非RISC架构环境中的高速数据和指令处理应用，并支持单处理器和多处理器系统中的高速处理应用。 优选的ICU有两条总线，一条用于处理器接口，另一条用于存储器接口。 ICU支持单个，突发和流水线处理器访问，并且能够在超过25兆赫的频率下工作，实现序列中第一次访问的两个周期的处理器访问时间，以及用于突发模式或直接访问的一个周期。 它可以用作具有灵活内部缓存组织的指令或数据缓存。 RISC处理器和两个ICU（用于指令和数据缓存）实现了一个非常高性能的处理器，具有16k字节的缓存。 可以通过使用附加的ICU来设计更大的高速缓存，根据本发明的优选实施例，它们是模块化的。 其他功能包括灵活且广泛的多处理器支持硬件，低功耗要求，以及支持总线监视，所有权方案，软件控制和硬件控制方案的组合，可与新型ICU一起使用以实现高速缓存的一致性。

公开(公告)号：US5166745A

公开(公告)日：1992-11-24

申请号：US517152

申请日：1990-05-01

申请人： William M. Johnson

发明人： William M. Johnson

IPC分类号： F41G3/32 ,  G01B11/27

CPC分类号： G01B11/27 ,  F41G3/323

摘要： Apparatus and method are disclosed enabling to register vectors respectively representative of directed energy pointing direction and targeted object pointing direction to allow rapid re-targeting boresight alignment transfer of a space-based neutral particle beam to targeted ballistic missile trajectories independently of relative reference frame vector measurement uncertainty arising from platform vibration and, among other things, space-noise.

摘要翻译： 公开的装置和方法能够记录分别代表定向能量指向方向和目标物体指向方向的矢量，以允许基于空间的中性粒子束的快速重新瞄准视线对准转移到独立于相对参考帧矢量测量的目标弹道导弹轨迹 平台振动引起的不确定性，以及空间噪声等。

公开(公告)号：US5129067A

公开(公告)日：1992-07-07

申请号：US361914

申请日：1989-06-06

申请人： William M. Johnson

发明人： William M. Johnson

IPC分类号： G06F9/30 ,  G06F9/34 ,  G06F9/38

CPC分类号： G06F9/382 ,  G06F9/30141 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3855

摘要： A multiple instruction decoder includes an input latch for receiving a plurality of logic instructions, wherein the plurality of logic instructions include N register-operand identifiers; arbitration logic coupled to the input latch for arbitrating read port contentions by the N register-operand identifiers for M available read ports (where M is less than N) based on arbitration data corresponding to each of the logic instructions, and for generating control signals indicative thereof; and a multiplexing unit for selectively supplying the N register-operand identifiers to the M available read ports in response to the control signals generated by the arbitration logic.

公开(公告)号：US5008796A

公开(公告)日：1991-04-16

申请号：US533973

申请日：1990-06-06

申请人： William M. Johnson

发明人： William M. Johnson

IPC分类号： H02M3/28 ,  H02M3/335

CPC分类号： H02M3/33523

摘要： A circuit for limiting the effect of overshoot in a transformer of the type having a primary winding and a secondary winding. The secondary winding is coupled to a load and the circuit has an output. An auxiliary or ballistic winding is operatively connected to the transformer and is adapted to generate a winding voltage which varies in response to a voltage generated across the primary winding. An electronic switch, preferably a transistor, is interposed between the ballistic winding and the output of the circuit. The switch is capable of being disposed in a first position or a second position. In one preferred embodiment, the winding voltage is communicated to the circuit output when the switch is in the first position. An actuating arrangement is coupled with both of the ballistic winding and the electronic switch. The electronic switch is disposed into the first position by the actuating arrangement a predetermined time interval after the winding voltage has exceeded a predetermined reference voltage. Accordingly, overshoot is eliminated in the output voltage of the circuit and load regulation of the transformer is improved.

公开(公告)号：US4851990A

公开(公告)日：1989-07-25

申请号：US12226

申请日：1987-02-09

申请人： William M. Johnson ,  Gigy Baror

发明人： William M. Johnson ,  Gigy Baror

IPC分类号： G06F13/16 ,  G06F9/32 ,  G06F12/06 ,  G06F13/18 ,  G06F13/42 ,  G06F15/78

CPC分类号： G06F13/4243 ,  G06F15/7835

摘要： Methods and apparatus for realizing a high performance interface between a processor, constituting part of a reduced instruction set computer (RISC) system, and a set of devices, including memory means. According to the invention, the interface includes three independent buses. A shared processor output bus, a processor input instruction bus, and a bidirectional data bus. The shared processor output address bus coupled the processor and the computer's memory. This bus carries both instructon and data access signals being transmitted by the processor to the memory. The processor input instruction bus also couples the processor and the computer's memory means, but carries instruction signals being transmitted from the memory to the processor. The bidirectional data bus provides a signal path for carrying data signals being transmitted by the memory to the processor and vice-a-versa. The novel interface uses demultiplexed buses for simpler timing and uses the separate data and instruction buses to provide extremely high transfer rates at a reasonable cost. The shared address bus accommodates pipelined and burst mode processor protocols with the burst mode protocol allowing concurrent data and instruction transfers. Methods and apparatus for controlling the buses and reporting bus status, etc., are also part of the invention and facilitate the implementation of features that include status reporting, handshaking between devices and the RISC processor, and bus arbitration.

公开(公告)号：US4811345A

公开(公告)日：1989-03-07

申请号：US942472

申请日：1986-12-16

申请人： William M. Johnson

发明人： William M. Johnson

IPC分类号： G06F11/22 ,  G06F11/267 ,  G06F11/273 ,  G06F11/30 ,  G06F11/00

CPC分类号： G06F11/2236 ,  G06F11/2733

摘要： Methods and apparatus are disclosed that facilitate the testing and development of computer systems that include at least one single chip microprocessor. In particular, a parallel test interface is described that allows an external test unit to (1) directly load instructions into the microprocessor under test utilizing the existing bus structure of the computer system; (2) step the processor through preselected test instruction sequences; (3) monitor processor states in both the processor's test and normal execution modes; and (4) halt and resume normal instruction processing. According to the invention, the microprocessor test interface comprises a plurality of dedicated CPU status output pins and a plurality of dedicated CPU control input pins, used by the test unit in combination with the existing bus structure of the computer system to provide the desired test facility for the single chip microprocessor. The preferred embodiment of the invention is realized in a RISC environment where the instruction lengths are fixed and the instruction processor has a single cycle execution time. Such an embodiment facilitates the direct insertion of instructions by the tester into the processor for decoding, without having to queue instructions or pass through complicated intervening hardware or test logic.

公开(公告)号：US4777588A

公开(公告)日：1988-10-11

申请号：US771311

申请日：1985-08-30

申请人： Brian W. Case ,  Rod G. Fleck ,  William M. Johnson ,  Cheng-Gang Kong ,  Ole Moller

发明人： Brian W. Case ,  Rod G. Fleck ,  William M. Johnson ,  Cheng-Gang Kong ,  Ole Moller

IPC分类号： G06F9/30 ,  G06F9/34 ,  G06F9/40 ,  G06F9/46 ,  G06F9/48 ,  G06F12/14

CPC分类号： G06F9/468 ,  G06F12/1458 ,  G06F9/4425 ,  G06F9/462

摘要： A high speed register file for use by an instruction processor suitable for reduced instruction-set computers (RISCs) is disclosed which is preferably used with an efficient register allocation method. The register file facilitates the passing of parameters between procedures by dynamically providing overlapping registers which are accessible to both procedures. Each procedure also has a set of "local" registers assigned to it which are inaccessible from other procedures. The register file is divided into a number of blocks and a protection register stores a word which proscribes access by a particular procedure or task to certain blocks. In this manner, an instruction processor using the register file can operate on multiple tasks maintaining the integrity of each from undesired changes occuring in the others.

摘要翻译： 公开了一种适用于精简指令集计算机（RISC）的指令处理器所使用的高速寄存器文件，其优选地以有效的寄存器分配方法使用。 寄存器文件通过动态地提供两个过程可访问的重叠寄存器来促进过程之间的参数传递。 每个过程也有一组分配给它的“本地”寄存器，不能从其他过程访问。 寄存器文件被分成多个块，并且保护寄存器存储一个单词，其禁止特定过程或任务访问某些块。 以这种方式，使用寄存器文件的指令处理器可以对多个任务进行操作，从而保持每个任务的完整性，而不是在其他任务中发生不希望的变化。

公开(公告)号：USD292587S

公开(公告)日：1987-11-03

申请号：US786044

申请日：1985-10-10

申请人： William M. Johnson

设计人： William M. Johnson