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    Nonvolatile memory devices and methods of operating the same
    71.
    发明申请
    Nonvolatile memory devices and methods of operating the same 有权
    非易失性存储器件及其操作方法

    公开(公告)号：US20080304328A1

    公开(公告)日：2008-12-11

    申请号：US12071451

    申请日：2008-02-21

    申请人： Young-gu Jin ,  Ki-ha Hong ,  Yoon-dong Park ,  Jai-kwang Shin ,  Suk-pil Kim

    发明人： Young-gu Jin ,  Ki-ha Hong ,  Yoon-dong Park ,  Jai-kwang Shin ,  Suk-pil Kim

    IPC分类号： G11C16/06 ,  H01L29/788

    CPC分类号： G11C16/0416 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/0673 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

    摘要： Example embodiments include nonvolatile memory devices that have good operation performance and may be made in a highly integrated structure, and methods of operating the same. Example embodiments of the nonvolatile memory devices include a substrate electrode, and a semiconductor channel layer on the substrate electrode, a floating gate electrode on the substrate electrode, wherein a portion of the floating gate electrode faces the semiconductor channel layer, a control gate electrode on the floating gate electrode, and wherein a distance between a portion of the floating gate electrode and the substrate electrode is smaller than a distance between the semiconductor channel layer and the substrate electrode wherein charge tunneling occurs.

    摘要翻译： 示例性实施例包括具有良好操作性能并且可以以高度集成的结构制造的非易失性存储器件及其操作方法。 非易失性存储器件的示例性实施例包括衬底电极和衬底电极上的半导体沟道层，衬底电极上的浮置栅电极，其中浮置栅电极的一部分面向半导体沟道层，控制栅极电极 所述浮置栅极电极，并且其中所述浮置栅电极的一部分与所述基板电极之间的距离小于半导体沟道层与发生电荷隧道的基板电极之间的距离。

    Non-volatile memory device having four storage node films and methods of operating and manufacturing the same
    72.
    发明申请
    Non-volatile memory device having four storage node films and methods of operating and manufacturing the same 审中-公开
    具有四个存储节点膜的非易失性存储器件及其操作和制造方法

    公开(公告)号：US20070296033A1

    公开(公告)日：2007-12-27

    申请号：US11704363

    申请日：2007-02-09

    申请人： Yoon-dong Park ,  Suk-pil Kim ,  Jae-woong Hyun

    发明人： Yoon-dong Park ,  Suk-pil Kim ,  Jae-woong Hyun

    IPC分类号： H01L27/12 ,  G11C11/34 ,  H01L21/84

    CPC分类号： H01L29/7887 ,  H01L29/42332 ,  H01L29/7851 ,  H01L29/7923

    摘要： A nonvolatile memory device that may operate in a multi-bit mode and a method of operating and manufacturing the nonvolatile memory device are provided. The nonvolatile memory device may include a first source region and a first drain region that are respectively in first fin portions on both sides of a control gate electrode and respectively separated from the control gate electrode, a second source region and a second drain region that are respectively formed in second fin portions on both sides of the control gate electrode and respectively separated from the control gate electrode, first and second storage node layers that are formed with the control gate electrode therebetween and on the side of the first fin opposite to a buried insulating layer between first and second fins, and third and fourth storage node layers that are formed with the control gate electrode therebetween and on the side of the second fin opposite to the buried insulating layer. The nonvolatile memory device may further include a semiconductor substrate including the first and second fins, a control gate electrode on the sides of the first and second fins opposite to the buried insulating layer and extending onto the buried insulating layer and a gate insulating layer between the first and second fins and the control gate electrode.

    摘要翻译： 提供了可以以多位模式操作的非易失性存储器件以及操作和制造非易失性存储器件的方法。 非易失性存储器件可以包括第一源极区域和第一漏极区域，其分别位于控制栅极电极的两侧的第一鳍片部分中，并且分别与控制栅极电极，第二源极区域和第二漏极区域分离 分别形成在控制栅电极的两侧的第二鳍部分中，并分别与控制栅电极分离，第一和第二存储节点层在其间形成有控制栅极电极，并且在第一鳍片的与掩埋 在第一和第二散热片之间的绝缘层，以及在其间形成有控制栅极电极的第三和第四存储节点层，以及在第二鳍片与掩埋绝缘层相对的一侧。 非易失性存储器件还可以包括：包括第一和第二鳍片的半导体衬底;在第一和第二鳍片的与掩埋绝缘层相对并且延伸到掩埋绝缘层上的侧面上的控制栅极电极和位于掩模绝缘层之间的栅极绝缘层 第一和第二鳍片和控制栅电极。

    Capacitorless DRAM and methods of manufacturing and operating the same
    74.
    发明申请
    Capacitorless DRAM and methods of manufacturing and operating the same 失效
    无电容DRAM及其制造和运行方法相同

    公开(公告)号：US20090065835A1

    公开(公告)日：2009-03-12

    申请号：US12153666

    申请日：2008-05-22

    申请人： Suk-pil Kim ,  Young-gu Jin ,  Yoon-dong Park

    发明人： Suk-pil Kim ,  Young-gu Jin ,  Yoon-dong Park

    IPC分类号： H01L29/00 ,  H01L21/336

    CPC分类号： H01L27/108 ,  H01L27/10802 ,  H01L29/7841

    摘要： Example embodiments provide a capacitorless dynamic random access memory (DRAM), and methods of manufacturing and operating the same. The capacitorless DRAM according to example embodiments may include a semiconductor layer separated from a top surface of a substrate and that contains a source region, a drain region, and a channel region, a charge reserving layer formed on the channel region, and a gate formed on the substrate to contact the channel region and the charge reserving layer.

    摘要翻译： 示例性实施例提供无电容器动态随机存取存储器（DRAM）及其制造和操作方法。 根据示例实施例的无电容器DRAM可以包括从衬底的顶表面分离并且包含源极区，漏极区和沟道区的半导体层，形成在沟道区上的电荷保留层，以及形成的栅极 在基板上与沟道区和电荷保留层接触。

    Non-volatile memory device and method of fabricating the same
    75.
    发明申请
    Non-volatile memory device and method of fabricating the same 审中-公开
    非易失性存储器件及其制造方法

    公开(公告)号：US20090273054A1

    公开(公告)日：2009-11-05

    申请号：US12382106

    申请日：2009-03-09

    申请人： Suk-pil Kim ,  Won-joo Kim ,  Seung-hoon Lee

    发明人： Suk-pil Kim ,  Won-joo Kim ,  Seung-hoon Lee

    IPC分类号： H01L29/68

    CPC分类号： H01L27/115 ,  H01L27/11206 ,  H01L27/24

    摘要： A non-volatile memory device and methods of fabricating the device according to example embodiments involve a stacked layer structure. The non-volatile memory device may include at least one first horizontal electrode including a first sidewall and a second sidewall; at least one second horizontal electrode including a third sidewall and a fourth sidewall; wherein the third sidewall may be disposed to face the first sidewall; at least one vertical electrode may be interposed between the first sidewall and the third sidewall, in such a way as to cross or intersect each of the at least one first and second horizontal electrodes, and; at least one data storage layer that may be capable of locally storing a change of electrical resistance may be interposed where the at least one first horizontal electrode and the at least one vertical electrode cross or intersect and where the at least one horizontal electrode and the at least one vertical electrodes cross or intersect.

    摘要翻译： 根据示例实施例的非易失性存储器件和制造器件的方法涉及堆叠层结构。 非易失性存储器件可以包括至少一个包括第一侧壁和第二侧壁的第一水平电极; 至少一个第二水平电极，包括第三侧壁和第四侧壁; 其中所述第三侧壁可以被设置为面对所述第一侧壁; 至少一个垂直电极可以插入在第一侧壁和第三侧壁之间，以便使得至少一个第一和第二水平电极中的每一个交叉或相交， 可以插入至少一个能够局部存储电阻变化的数据存储层，其中至少一个第一水平电极和至少一个垂直电极交叉或相交，并且其中至少一个水平电极和at 至少一个垂直电极交叉或相交。

    Capacitorless DRAM and methods of manufacturing and operating the same
    77.
    发明授权
    Capacitorless DRAM and methods of manufacturing and operating the same 失效
    无电容DRAM及其制造和运行方法相同

    公开(公告)号：US08053822B2

    公开(公告)日：2011-11-08

    申请号：US12153666

    申请日：2008-05-22

    申请人： Suk-pil Kim ,  Young-gu Jin ,  Yoon-dong Park

    发明人： Suk-pil Kim ,  Young-gu Jin ,  Yoon-dong Park

    IPC分类号： H01L27/108

    CPC分类号： H01L27/108 ,  H01L27/10802 ,  H01L29/7841

    摘要： Example embodiments provide a capacitorless dynamic random access memory (DRAM), and methods of manufacturing and operating the same. The capacitorless DRAM according to example embodiments may include a semiconductor layer separated from a top surface of a substrate and that contains a source region, a drain region, and a channel region, a charge reserving layer formed on the channel region, and a gate formed on the substrate to contact the channel region and the charge reserving layer.

    摘要翻译： 示例性实施例提供无电容器动态随机存取存储器（DRAM）及其制造和操作方法。 根据示例实施例的无电容器DRAM可以包括从衬底的顶表面分离并且包含源极区，漏极区和沟道区的半导体层，形成在沟道区上的电荷保留层，以及形成的栅极 在基板上与沟道区和电荷保留层接触。

    Nonvolatile memory devices and methods of operating the same
    78.
    发明授权
    Nonvolatile memory devices and methods of operating the same 有权
    非易失性存储器件及其操作方法

    公开(公告)号：US07948019B2

    公开(公告)日：2011-05-24

    申请号：US12071451

    申请日：2008-02-21

    申请人： Young-gu Jin ,  Ki-ha Hong ,  Yoon-dong Park ,  Jai-kwang Shin ,  Suk-pil Kim

    发明人： Young-gu Jin ,  Ki-ha Hong ,  Yoon-dong Park ,  Jai-kwang Shin ,  Suk-pil Kim

    IPC分类号： H01L29/788

    CPC分类号： G11C16/0416 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/0673 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

    摘要： Example embodiments include nonvolatile memory devices that have good operation performance and may be made in a highly integrated structure, and methods of operating the same. Example embodiments of the nonvolatile memory devices include a substrate electrode, and a semiconductor channel layer on the substrate electrode, a floating gate electrode on the substrate electrode, wherein a portion of the floating gate electrode faces the semiconductor channel layer, a control gate electrode on the floating gate electrode, and wherein a distance between a portion of the floating gate electrode and the substrate electrode is smaller than a distance between the semiconductor channel layer and the substrate electrode wherein charge tunneling occurs.

    摘要翻译： 示例性实施例包括具有良好操作性能并且可以以高度集成的结构制造的非易失性存储器件及其操作方法。 非易失性存储器件的示例性实施例包括衬底电极和衬底电极上的半导体沟道层，衬底电极上的浮置栅电极，其中浮置栅电极的一部分面向半导体沟道层，控制栅极电极 所述浮置栅极电极，并且其中所述浮置栅电极的一部分与所述基板电极之间的距离小于半导体沟道层与发生电荷隧道的基板电极之间的距离。

    COLUMNAR NON-VOLATILE MEMORY DEVICES WITH AUXILIARY TRANSISTORS AND METHODS OF OPERATING THE SAME
    79.
    发明申请
    COLUMNAR NON-VOLATILE MEMORY DEVICES WITH AUXILIARY TRANSISTORS AND METHODS OF OPERATING THE SAME 有权
    具有辅助晶体管的柱状非易失性存储器件及其操作方法

    公开(公告)号：US20100067301A1

    公开(公告)日：2010-03-18

    申请号：US12493935

    申请日：2009-06-29

    申请人： Suk-pil Kim ,  Yoon-dong Park

    发明人： Suk-pil Kim ,  Yoon-dong Park

    IPC分类号： G11C16/04 ,  H01L29/792

    CPC分类号： H01L21/28273 ,  G11C16/10 ,  H01L21/28282 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7883 ,  H01L29/792 ,  H01L29/7926

    摘要： A non-volatile memory device includes at least one semiconductor column having a first sidewall and a second sidewall. The device also includes at least one gate electrode is disposed on the first sidewall and at least one control gate electrode disposed on the second sidewall. The device further includes at least one charge storage layer is disposed between the second sidewall and the at least one control gate electrode. The at least one gate electrode and the at least one control gate electrode may be disposed on opposite sides of the at least one semiconductor column such that they commonly control a channel region in the semiconductor column.

    摘要翻译： 非易失性存储器件包括至少一个具有第一侧壁和第二侧壁的半导体柱。 该器件还包括设置在第一侧壁上的至少一个栅电极和设置在第二侧壁上的至少一个控制栅电极。 该装置还包括至少一个电荷存储层设置在第二侧壁和至少一个控制栅电极之间。 至少一个栅电极和至少一个控制栅电极可以设置在至少一个半导体柱的相对侧上，使得它们共同地控制半导体柱中的沟道区。