公开(公告)号：US20110152423A1

公开(公告)日：2011-06-23

申请号：US12646364

申请日：2009-12-23

申请人： Ning Lu ,  Sigfredo Gonzalez ,  Emie M. Silvestre ,  Geng Wang

发明人： Ning Lu ,  Sigfredo Gonzalez ,  Emie M. Silvestre ,  Geng Wang

IPC分类号： C08K5/541 ,  C08L43/02

CPC分类号： C08F220/26 ,  A61K8/8152 ,  A61K2800/54 ,  A61Q1/02 ,  A61Q5/12 ,  C08F220/38 ,  C08F230/02

摘要： The present invention is directed to a network composition the reaction product of: (i) at least one anionic polymerizable ethylenically unsaturated monomer (I) selected from the group consisting of [CH2═C(R3)C(O)OXa(C2H4O)b(C3H6O)c(C4H8O)d]pP(O)(OY)q(OZ)r where R3═H or alkyl of 1 to about 6 carbon atoms; X=alkyl, aryl, or alkaryl diradical connecting group of 0 to about 9 carbon atoms; a is 0 to about 100; b is 0 to about 100;c is 0 to about 100; d is 0 to about 100; q is 0 to about 2; r is 0 to about 2; p is 1 to about 3 subject to the limitation that p+q+r=3; and Y and Z is H, or metal ion; and CH2═C(R3)C(O)OXa′(C2H4O)b′(C3H6O)c′(C4H8O)d′—SO3—Y) where R3═H or alkyl of from 1 to about 6 carbon atoms; X=alkyl, aryl, or alkaryl diradical connecting group of 0 to about 9 carbon atoms; a′ is 0 to about 100; b′ is 0 to about 100; c′ is 0 to about 100; d′ is 0 to about 100; Y is H, or metal ion; and (ii) one or more additional monomers (II) selected from the group consisting of acrylic acid/acrylate, methacrylic acid/methacrylate, acrylamides, vinyl acetate and styrene, which are copolymerizable with (I); and (iii) a cross-linking agent (III), capable of copolymerizing with (I) and (II).

摘要翻译： 本发明涉及一种网络组合物，其反应产物为：（i）至少一种选自[CH 2 = C（R 3）C（O）O X a（C 2 H 4 O）b的阴离子可聚合烯属不饱和单体（I） （C 3 H 6 O）c（C 4 H 8 O）d] pP（O）（OY）q（OZ）r其中R 3 = H或1至约6个碳原子的烷基; X = 0至约9个碳原子的烷基，芳基或烷芳基双基连接基团; a为0〜100; b为0至约100; c为0至约100; d为0至约100; q为0〜2; r为0〜2; p为1至约3，但受限于p + q + r = 3; Y和Z是H或金属离子; （C 3 H 6 O）c'（C 4 H 8 O）d-SO 3-Y）其中R 3 = H或1至约6个碳原子的烷基; X = 0至约9个碳原子的烷基，芳基或烷芳基双基连接基团; a'为0至约100; b'为0至约100; c'为0至约100; d'为0至约100; Y是H或金属离子; 和（ii）可与（I）共聚的一种或多种选自丙烯酸/丙烯酸酯，甲基丙烯酸/甲基丙烯酸酯，丙烯酰胺，乙酸乙烯酯和苯乙烯的另外的单体（II）; 和（iii）能够与（I）和（II）共聚的交联剂（III）。

公开(公告)号：US20100283093A1

公开(公告)日：2010-11-11

申请号：US12437242

申请日：2009-05-07

申请人： Chengwen Pei ,  Kangguo Cheng ,  Herbert L. Ho ,  Subramanian S. Iyer ,  Byeong Y. Kim ,  Geng Wang ,  Huilong Zhu

发明人： Chengwen Pei ,  Kangguo Cheng ,  Herbert L. Ho ,  Subramanian S. Iyer ,  Byeong Y. Kim ,  Geng Wang ,  Huilong Zhu

IPC分类号： H01L27/10 ,  H01L21/02

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/10861 ,  H01L29/945

摘要： A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.

摘要翻译： 提供了一种存储器件，其在一个实施例中包括位于半导体衬底中的沟槽电容器，该半导体衬底包括由半导体衬底提供的外部电极，由导电填充材料提供的内部电极，以及位于外部电极和 内电极 以及位于沟槽电容器上方的半导体器件。 半导体器件包括源极区，漏极区和栅极结构，其中半导体器件形成在通过介电层与半导体衬底分离的半导体层上。 存在从半导体层的上表面延伸到与半导体衬底电接触的第一接触，以及从半导体器件的漏极区域与至少一个沟槽内的导电材料电接触的第二接触。

公开(公告)号：US07791124B2

公开(公告)日：2010-09-07

申请号：US12124186

申请日：2008-05-21

申请人： Kangguo Cheng ,  Herbert L. Ho ,  Paul C. Parries ,  Geng Wang

发明人： Kangguo Cheng ,  Herbert L. Ho ,  Paul C. Parries ,  Geng Wang

IPC分类号： H01L27/108

CPC分类号： H01L29/945 ,  H01L21/84 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/66181

摘要： A bottle shaped trench for an SOI capacitor is formed by a simple processing sequence. A non-conformal dielectric layer with an optional conformal dielectric diffusion barrier layer underneath is formed on sidewalls of a deep trench. Employing an isotropic etch, the non-conformal dielectric layer is removed from a bottom portion of the deep trench, leaving a dielectric spacer covering sidewalls of the buried insulator layer and the top semiconductor layer. The bottom portion of the deep trench is expanded to form a bottle shaped trench, and a buried plated is formed underneath the buried insulator layer. The dielectric spacer may be recessed during formation of a buried strap to form a graded thickness dielectric collar around the upper portion of an inner electrode. Alternately, the dielectric spacer may be removed prior to formation of a buried strap.

摘要翻译： 用于SOI电容器的瓶形沟槽通过简单的处理顺序形成。 在深沟槽的侧壁上形成具有可选的适形电介质扩散阻挡层的非保形介电层。 采用各向同性蚀刻，从深沟槽的底部去除非共形电介质层，留下覆盖掩埋绝缘体层和顶部半导体层的侧壁的电介质间隔物。 深沟槽的底部被膨胀以形成瓶形沟槽，并且在掩埋绝缘体层的下方形成埋入的电镀层。 在形成掩埋带的过程中，电介质间隔物可以是凹陷的，以形成围绕内电极的上部的分级厚度的介质环。 或者，可以在形成掩埋带之前去除电介质间隔物。

公开(公告)号：US07776706B2

公开(公告)日：2010-08-17

申请号：US12169727

申请日：2008-07-09

申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Herbert L. Ho ,  Geng Wang

发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Herbert L. Ho ,  Geng Wang

IPC分类号： H01L21/8234

CPC分类号： H01L27/10867 ,  H01L27/0207

摘要： A method of forming a trench memory cell includes forming a trench capacitor within a substrate material, the trench capacitor including a node dielectric layer formed within a trench and a conductive capacitor electrode material formed within the trench in contact with the node dielectric layer; forming a strap mask so as cover one side of the trench and removing one or more materials from an uncovered opposite side of the trench; and forming a conductive buried strap material within the trench; wherein the strap mask is patterned in a manner such that a single-sided buried strap is defined within the trench, the single-sided buried strap configured in a manner such that the deep trench capacitor is electrically accessible at only one side of the trench.

摘要翻译： 形成沟槽存储单元的方法包括在衬底材料内形成沟槽电容器，所述沟槽电容器包括形成在沟槽内的节点电介质层和形成在所述沟槽内与所述节点电介质层接触的导电电容器电极材料; 形成带状掩模，以覆盖沟槽的一侧，并从沟槽的未覆盖的相对侧移除一种或多种材料; 以及在所述沟槽内形成导电掩埋带材料; 其中所述带掩模被图案化，使得在所述沟槽内限定单面掩埋带，所述单侧埋入带以使得所述深沟槽电容器仅在所述沟槽的一侧电可访问的方式构造。

公开(公告)号：US20100203732A1

公开(公告)日：2010-08-12

申请号：US12368561

申请日：2009-02-10

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Geng Wang

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Geng Wang

IPC分类号： H01L21/302 ,  H01L21/30 ,  H01L21/308

CPC分类号： H01L21/0338 ,  H01L21/0337 ,  H01L21/26586 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/32134 ,  H01L21/32135 ,  H01L29/66795 ,  Y10S438/942 ,  Y10S438/947

摘要： A semiconductor device is formed by providing a substrate and forming a semiconductor-containing layer atop the substrate. A mask having a plurality of openings is then formed atop the semiconductor-containing layer, wherein adjacent openings of the plurality of openings of the mask are separated by a minimum feature dimension. Thereafter, an angled ion implantation is performed to introduce dopants to a first portion of the semiconductor-containing layer, wherein a remaining portion that is substantially free of dopants is present beneath the mask. The first portion of the semiconductor-containing layer containing the dopants is removed selective to the remaining portion of semiconductor-containing layer that is substantially free of the dopants to provide a pattern of sublithographic dimension, and the pattern is transferred into the substrate to provide a fin structure of sublithographic dimension.

摘要翻译： 通过提供衬底并在衬底上形成含半导体的层来形成半导体器件。 然后在半导体含有层顶上形成具有多个开口的掩模，其中掩模的多个开口中的相邻开口被最小特征尺寸分开。 此后，进行成角度的离子注入以将掺杂剂引入到半导体含有层的第一部分，其中基本上不含掺杂剂的剩余部分存在于掩模下方。 含有掺杂剂的含半导体层的第一部分被选择性地除去基本上不含掺杂剂的半导体含有层的剩余部分，以提供亚光刻尺寸的图案，并且将图案转移到衬底中以提供 翅片结构的亚光刻尺寸。

公开(公告)号：US20100200949A1

公开(公告)日：2010-08-12

申请号：US12370024

申请日：2009-02-12

申请人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Robert Hannon ,  Ravi M. Todi ,  Geng Wang

发明人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Robert Hannon ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L29/94 ,  H01L21/334

CPC分类号： H01L29/945 ,  H01L27/0605 ,  H01L27/0733 ,  H01L27/1203 ,  H01L28/90 ,  H01L29/66181

摘要： A method of forming a deep trench capacitor includes providing a wafer. Devices are formed on a front side of the wafer. A through-silicon-via is formed on a substrate of the wafer. Deep trenches are formed on a back side of the wafer. A deep trench capacitor is formed in the deep trench. The through-silicon-via connects the deep trench capacitor to the devices.

摘要翻译： 形成深沟槽电容器的方法包括提供晶片。 器件形成在晶片的前侧。 在晶片的基板上形成贯通硅通孔。 深沟槽形成在晶片的背面。 在深沟槽中形成深沟槽电容器。 直通硅通孔将深沟槽电容器连接到器件。

公开(公告)号：US20090289291A1

公开(公告)日：2009-11-26

申请号：US12124186

申请日：2008-05-21

申请人： Kangguo Cheng ,  Herbert L. Ho ,  Paul C. Parries ,  Geng Wang

发明人： Kangguo Cheng ,  Herbert L. Ho ,  Paul C. Parries ,  Geng Wang

IPC分类号： H01L29/94 ,  H01L21/20

CPC分类号： H01L29/945 ,  H01L21/84 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/66181

摘要： A bottle shaped trench for an SOI capacitor is formed by a simple processing sequence. A non-conformal dielectric layer with an optional conformal dielectric diffusion barrier layer underneath is formed on sidewalls of a deep trench. Employing an isotropic etch, the non-conformal dielectric layer is removed from a bottom portion of the deep trench, leaving a dielectric spacer covering sidewalls of the buried insulator layer and the top semiconductor layer. The bottom portion of the deep trench is expanded to form a bottle shaped trench, and a buried plated is formed underneath the buried insulator layer. The dielectric spacer may be recessed during formation of a buried strap to form a graded thickness dielectric collar around the upper portion of an inner electrode. Alternately, the dielectric spacer may be removed prior to formation of a buried strap.

摘要翻译： 用于SOI电容器的瓶形沟槽通过简单的处理顺序形成。 在深沟槽的侧壁上形成具有可选的适形电介质扩散阻挡层的非保形介电层。 采用各向同性蚀刻，从深沟槽的底部去除非共形电介质层，留下覆盖掩埋绝缘体层和顶部半导体层的侧壁的电介质间隔物。 深沟槽的底部被膨胀以形成瓶形沟槽，并且在掩埋绝缘体层的下方形成埋入的电镀层。 在形成掩埋带的过程中，电介质间隔物可以是凹陷的，以形成围绕内电极的上部的分级厚度的介质环。 或者，可以在形成掩埋带之前去除电介质间隔物。

公开(公告)号：US07596038B2

公开(公告)日：2009-09-29

申请号：US11954468

申请日：2007-12-12

申请人： Hoki Kim ,  Geng Wang

发明人： Hoki Kim ,  Geng Wang

IPC分类号： G11C11/406 ,  G11C11/24

CPC分类号： G11C11/406 ,  G11C2211/4016 ,  G11C2211/4065

摘要： A system including a DRAM memory device on an integrated circuit (IC) using a control logic device to initiate a body refresh operation to provide a means for maintaining a low voltage at a floating body and discourage data loss, and a design structure including the DRAM memory device embodied in a machine readable medium is provided. A plurality of DRAM cells are connected to a first word line circuit and a first bit line circuit. The control logic device is coupled to the DRAM memory device and the IC for initiating the body refresh cycle. The control logic communicates with a first bit line and word line circuits and communicates with a reference word line and bit line circuits. A sense amplifier circuit and signal is provided for amplifying the voltage at the first bit line and the reference bit line. The body refresh cycle includes deactivating the first word line voltage while the first bit line and reference bit line voltages continue.

摘要翻译： 一种系统，包括使用控制逻辑装置的集成电路（IC）上的DRAM存储器件，以启动身体刷新操作，以提供用于在浮体保持低电压并阻止数据丢失的装置，以及包括DRAM的设计结构 提供了体现在机器可读介质中的存储设备。 多个DRAM单元连接到第一字线电路和第一位线电路。 控制逻辑器件耦合到DRAM存储器件和用于启动器件刷新周期的IC。 控制逻辑与第一位线和字线电路通信，并与参考字线和位线电路进行通信。 提供读出放大器电路和信号用于放大第一位线和参考位线处的电压。 身体刷新周期包括在第一位线和参考位线电压持续时停用第一字线电压。

公开(公告)号：US20090176339A1

公开(公告)日：2009-07-09

申请号：US12316748

申请日：2008-12-16

申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Jack A. Mandelman ,  Carl J. Radens ,  Geng Wang

发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Jack A. Mandelman ,  Carl J. Radens ,  Geng Wang

IPC分类号： H01L21/8242

CPC分类号： G11C8/16 ,  G11C11/405 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10861

摘要： A method is provided for fabricating a multi-port memory in which a plurality of parallel connected capacitors are in a cell. A plurality of trench capacitors are formed which have capacitor dielectric layers extending along walls of the plurality of trenches, the plurality of trench capacitors having first capacitor plates and second capacitor plates opposite the capacitor dielectric layers from the first capacitor plates. The first capacitor plates are conductively tied together and the second capacitor plates are conductively tied together. In this way, the first capacitor plates are adapted to receive a same variable voltage and the second capacitor plates are adapted to receive a same fixed voltage.

摘要翻译： 提供了一种用于制造其中多个并联电容器在单元中的多端口存储器的方法。 形成多个沟槽电容器，其具有沿多个沟槽的壁延伸的电容器电介质层，所述多个沟槽电容器具有第一电容器板和与第一电容器板相对的电容器电介质层的第二电容器板。 第一电容器板导电地连接在一起，并且第二电容器板被导电地连接在一起。 以这种方式，第一电容器板适于接收相同的可变电压，并且第二电容器板适于接收相同的固定电压。

公开(公告)号：US07550359B1

公开(公告)日：2009-06-23

申请号：US12116626

申请日：2008-05-07

申请人： Kangguo Cheng ,  Herbert L. Ho ,  Geng Wang

发明人： Kangguo Cheng ,  Herbert L. Ho ,  Geng Wang

IPC分类号： H01L21/00

CPC分类号： H01L27/1203 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1087 ,  H01L29/66181

摘要： A method for fabricating silicon-on-insulator (SOI) trench memory includes forming a trench on a substrate, wherein a buried oxide layer is disposed on the substrate, a SOI layer is disposed on the buried oxide layer, and a hardmask layer is disposed on the SOI layer, implanting ions into the substrate and the SOI layer on a first opposing side of the trench and a second opposing side the trench to partially form a capacitor, depositing a node dielectric in the trench, filling the trench with a first polysilicon, removing a portion of the first polysilicon from the trench, removing an exposed portion of the node dielectric, filling the trench with a second polysilicon, masking to define an active region on the hardmask layer, forming shallow trench isolation (STI) such that the STI contacts a portion of the buried oxide layer, removing the hardmask layer, and forming a transistor.

摘要翻译： 一种用于制造绝缘体上硅（SOI）沟槽存储器的方法，包括在衬底上形成沟槽，其中掩埋氧化物层设置在衬底上，SOI层设置在掩埋氧化物层上，并且设置硬掩模层 在所述SOI层上，将离子注入到所述衬底中并且在所述沟槽的第一相对侧上的所述SOI层和所述沟槽的第二相对侧，以部分地形成电容器，在所述沟槽中沉积节点电介质，用第一多晶硅填充所述沟槽 从所述沟槽去除所述第一多晶硅的一部分，去除所述节点电介质的暴露部分，用第二多晶硅填充所述沟槽，以掩蔽以限定所述硬掩模层上的有源区域，形成浅沟槽隔离（STI），使得 STI接触掩埋氧化物层的一部分，去除硬掩模层，并形成晶体管。