公开(公告)号：US06825698B2

公开(公告)日：2004-11-30

申请号：US10229342

申请日：2002-08-26

申请人： Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Philip Pan

发明人： Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Philip Pan

IPC分类号： H03B100

CPC分类号： H03K19/17744 ,  H03K19/0175 ,  H03K19/017509 ,  H03K19/017581 ,  H03K19/1774 ,  H03K19/17788

摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.

摘要翻译： 提供高速或低速灵活的输入和输出的方法和设备。 提供具有高速输入，高速输出，低速或中速输入以及低速或中速输出的输入和输出结构。 选择其中一个输入和输出电路，并取消选择其他电路。 高速输入和输出电路相当简单，在一个示例中，仅具有用于控制线路输入的清除信号，并且能够与集成电路的核心内的低速电路接口。 低速或中速输入和输出电路比较灵活，例如具有预置，使能和清除作为控制线路输入，并且能够支持JTAG边界测试。 这些并行高速和低速电路是用户可选择的，使得输入输出结构根据应用的要求在速度和功能之间进行优化。

公开(公告)号：US08384460B1

公开(公告)日：2013-02-26

申请号：US13420349

申请日：2012-03-14

申请人： Chiakang Sung ,  John Henry Bui ,  Khai Nguyen ,  Bonnie I. Wang ,  Xiaobao Wang

发明人： Chiakang Sung ,  John Henry Bui ,  Khai Nguyen ,  Bonnie I. Wang ,  Xiaobao Wang

IPC分类号： H03H11/16

CPC分类号： H03L7/0814 ,  H03K2005/00293

摘要： An adjustable delay circuit includes first and second transistors each having a control input coupled to an input node of the adjustable delay circuit and an output coupled to an output node of the adjustable delay circuit. The adjustable delay circuit includes a first pass gate coupled between first and second capacitors and the output node of the adjustable delay circuit. The first and the second capacitors are coupled between a node at a high voltage and a node at a low voltage. The first pass gate is operable to be controlled by a first delay control signal.

摘要翻译： 可调延迟电路包括第一和第二晶体管，每个晶体管具有耦合到可调延迟电路的输入节点的控制输入和耦合到可调延迟电路的输出节点的输出。 可调延迟电路包括耦合在第一和第二电容器之间的第一通过栅极和可调延迟电路的输出节点。 第一和第二电容器耦合在高电压节点和低电压节点之间。 第一通过门可操作以由第一延迟控制信号控制。

公开(公告)号：US08149038B1

公开(公告)日：2012-04-03

申请号：US12729114

申请日：2010-03-22

申请人： Chiakang Sung ,  John Henry Bui ,  Khai Nguyen ,  Bonnie I. Wang ,  Xiaobao Wang

发明人： Chiakang Sung ,  John Henry Bui ,  Khai Nguyen ,  Bonnie I. Wang ,  Xiaobao Wang

IPC分类号： H03H11/16

CPC分类号： H03L7/0814 ,  H03K2005/00293

摘要： A dynamic phase alignment circuit includes a phase generator circuit having delay-locked loop circuits that generate periodic output signals. Each of the delay-locked loop circuits generates one of the periodic output signals in response to at least two periodic input signals. A multiplexer circuit selects a selected periodic signal from among the periodic input signals and the periodic output signals based on select signals. A phase detection circuit compares a phase of the selected periodic signal to a data signal to generate a phase detection signal. A control logic circuit generates the select signals. The control logic circuit adjusts the select signals based on changes in the phase detection signal to cause the multiplexer circuit to adjust the phase of the selected periodic signal.

摘要翻译： 动态相位对准电路包括具有产生周期性输出信号的延迟锁定环路电路的相位发生器电路。 每个延迟锁定环路电路响应于至少两个周期性输入信号产生周期性输出信号之一。 多路复用器电路基于选择信号从周期性输入信号和周期性输出信号中选择选定的周期信号。 相位检测电路将选择的周期信号的相位与数据信号进行比较，以产生相位检测信号。 控制逻辑电路产生选择信号。 控制逻辑电路基于相位检测信号的变化来调整选择信号，以使多路复用器电路调整所选周期信号的相位。

公开(公告)号：US20070236247A1

公开(公告)日：2007-10-11

申请号：US11381356

申请日：2006-05-02

申请人： Xiaobao Wang ,  Chiakang Sung ,  Khai Nguyen

发明人： Xiaobao Wang ,  Chiakang Sung ,  Khai Nguyen

IPC分类号： H03K17/16

CPC分类号： G11C7/1048 ,  G11C2207/2254 ,  H03H11/30 ,  H04L25/0278 ,  H04L25/0292

摘要： On-chip termination (OCT)calibration techniques are provided that support input/output (IO) banks on an integrated circuit (IC) using OCT controllers. The OCT controllers calibrate the on-chip termination impedance in the IO banks using a shared parallel bus or separate parallel buses. Multiplexers or select logic in each IO bank select control signals from the OCT controllers in response to select signals. According to some embodiments, each of the IO banks on an IC can receive OCT control signals from any of the OCT controllers on the IC.

摘要翻译： 提供使用OCT控制器在集成电路（IC）上支持输入/输出（IO）组的片上终止（OCT）校准技术。 OCT控制器使用共享并行总线或单独的并行总线校准IO组中的片上终端阻抗。 每个IO组中的多路复用器或选择逻辑根据选择信号选择来自OCT控制器的控制信号。 根据一些实施例，IC上的每个IO组可以从IC上的任何OCT控制器接收OCT控制信号。

公开(公告)号：US07525360B1

公开(公告)日：2009-04-28

申请号：US11735401

申请日：2007-04-13

申请人： Xiaobao Wang ,  Chiakang Sung ,  Khai Nguyen

发明人： Xiaobao Wang ,  Chiakang Sung ,  Khai Nguyen

IPC分类号： H03K3/017

CPC分类号： G11C7/22 ,  G06F1/10 ,  G11C7/1051 ,  G11C7/1066 ,  H03K5/04 ,  H03K5/133 ,  H03K5/1565 ,  H03K2005/00058

摘要： Circuits, methods and apparatus are provided to control the duty cycle of a signal. The rising and falling edges of a signal can be delayed independently to provide the selection or tuning of the duty cycle of the signal. Additionally, the delays can be used to reduce skew among both edges of signals being provided or transmitted by a data interface. The delays can be made to not cause a high-Z during a transition of the signal.

摘要翻译： 提供电路，方法和装置来控制信号的占空比。 可以独立地延迟信号的上升沿和下降沿以提供信号占空比的选择或调谐。 此外，延迟可以用于减少由数据接口提供或发送的信号的两个边缘之间的偏差。 可以在信号转换期间延迟不会引起高电平。

公开(公告)号：US06603329B1

公开(公告)日：2003-08-05

申请号：US10044459

申请日：2002-01-11

申请人： Xiaobao Wang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen

发明人： Xiaobao Wang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen

IPC分类号： H03K1716

CPC分类号： H04L25/0278 ,  H04L25/0298

摘要： Techniques for on-chip impedance termination are provided that substantially reduce the number of external resistors that are need to provide impedance termination at a plurality of pairs of differential input/output (I/O) pins. On-chip impedance termination circuits of the present invention may include an amplifier, a feedback loop, and an impedance termination circuit. A reference voltage is provided to a first input terminal of the amplifier. A feedback loop is coupled between an output terminal of the amplifier and a second input terminal of the amplifier. The amplifier drives its output voltage so that the voltage at the second input terminal matches the voltage at the first input terminal. The output voltage of the amplifier determines the resistance of the impedance termination circuit. The impedance termination circuit is coupled between differential I/O pins.

摘要翻译： 提供用于片上阻抗终止的技术，其大大减少了需要在多对差分输入/输出（I / O）引脚上提供阻抗终端的外部电阻器的数量。 本发明的片上阻抗终端电路可以包括放大器，反馈回路和阻抗终端电路。 将参考电压提供给放大器的第一输入端。 反馈回路耦合在放大器的输出端和放大器的第二输入端之间。 放大器驱动其输出电压，使得第二输入端子处的电压与第一输入端子处的电压匹配。 放大器的输出电压决定了阻抗终端电路的电阻。 阻抗端接电路耦合在差分I / O引脚之间。

公开(公告)号：US08610462B1

公开(公告)日：2013-12-17

申请号：US13332730

申请日：2011-12-21

申请人： Xiaobao Wang ,  Chiakang Sung ,  Khai Nguyen ,  Bonnie I. Wang

发明人： Xiaobao Wang ,  Chiakang Sung ,  Khai Nguyen ,  Bonnie I. Wang

IPC分类号： H03K19/094 ,  H03K19/0175 ,  H03K3/00 ,  H03B1/00

CPC分类号： H03K3/356113

摘要： Circuits and techniques for operating an integrated circuit (IC) with a level shifter circuit are disclosed. A level shifter circuit with input and output terminals is operable to shift an input signal that ranges from a ground voltage to a first positive voltage to an output signal that ranges from the ground voltage to a second positive voltage. The level shifter circuit further includes a first kicker transistor having a first source-drain terminal operable to receive a buffered version of the input signal and having a second source-drain terminal coupled to the output terminal. The first kicker transistor may receive gate signals that turn on the first kicker transistor when the input signal is at the ground voltage and may pull the output terminal to the first positive voltage as the input signal transitions from the ground voltage to the first positive voltage.

摘要翻译： 公开了用于利用电平移位器电路来操作集成电路（IC）的电路和技术。 具有输入和输出端子的电平移位器电路可操作以将从地电压到第一正电压的输入信号移动到范围从接地电压到第二正电压的输出信号。 电平移位器电路还包括具有第一源极 - 漏极端子的第一汲取晶体管，第一源极 - 漏极端子可操作以接收缓冲版本的输入信号并具有耦合到输出端子的第二源极 - 漏极端子。 当输入信号处于接地电压时，第一icker晶体晶体管可以接收导通第一猝发晶体管的栅极信号，并且当输入信号从接地电压转变到第一正电压时，可以将输出端拉至第一正电压。

公开(公告)号：US07994821B1

公开(公告)日：2011-08-09

申请号：US12753389

申请日：2010-04-02

申请人： Xiaobao Wang ,  Chiakang Sung ,  Khai Nguyen

发明人： Xiaobao Wang ,  Chiakang Sung ,  Khai Nguyen

IPC分类号： H03K19/0175

CPC分类号： H03K3/356069

摘要： A level shifter circuit includes first and second transistors coupled in series and third and fourth transistors coupled in series. The fourth transistor is coupled to a first node between the first and the second transistors. The level shifter circuit also includes fifth and sixth transistors coupled in series and seventh and eighth transistors coupled in series. The eighth transistor is coupled to a second node between the fifth and the sixth transistors. The second and the eighth transistors receive a first input signal at control inputs. The fourth and the sixth transistors receive a second input signal at control inputs. The second input signal is inverted relative to the first input signal.

摘要翻译： 电平移位器电路包括串联耦合的第一和第二晶体管，以及串联耦合的第三和第四晶体管。 第四晶体管耦合到第一和第二晶体管之间的第一节点。 电平移位器电路还包括串联耦合的第五和第六晶体管，以及串联耦合的第七和第八晶体管。 第八晶体管耦合到第五和第六晶体管之间的第二节点。 第二和第八晶体管在控制输入端接收第一输入信号。 第四和第六晶体管在控制输入端接收第二输入信号。 第二输入信号相对于第一输入信号反相。

公开(公告)号：US07973553B1

公开(公告)日：2011-07-05

申请号：US12721759

申请日：2010-03-11

申请人： Xiaobao Wang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen ,  John Henry Bui

发明人： Xiaobao Wang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen ,  John Henry Bui

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H04L25/0278

摘要： A circuit includes first transistors and a comparator. The comparator compares a reference signal and a signal that is based on conductive states of the first transistors. A control circuit generates first control signals based on an output signal of the comparator. The conductive states of the first transistors are determined based on the first control signals. An arithmetic circuit performs an arithmetic function based on the first control signals and second control signals to generate calibration signals. Second transistors provide a termination impedance at an external terminal of the circuit that is based on the calibration signals.

摘要翻译： 电路包括第一晶体管和比较器。 比较器比较参考信号和基于第一晶体管的导电状态的信号。 控制电路根据比较器的输出信号产生第一控制信号。 基于第一控制信号来确定第一晶体管的导通状态。 算术电路基于第一控制信号和第二控制信号执行运算功能，以生成校准信号。 第二晶体管在基于校准信号的电路的外部端子处提供终端阻抗。

公开(公告)号：US07551014B1

公开(公告)日：2009-06-23

申请号：US11670109

申请日：2007-02-01

申请人： Bonnie I. Wang ,  Chiakang Sung ,  Khai Nguyen ,  Xiaobao Wang

发明人： Bonnie I. Wang ,  Chiakang Sung ,  Khai Nguyen ,  Xiaobao Wang

IPC分类号： G06F7/44

CPC分类号： H04L25/0272

摘要： Circuits and methods provide single-ended and differential signals. Single-ended drivers are used to, e.g., reduce pin capacitance. The output cell uses an inversion circuit, such as a phase splitter, to derive the differential signals from the same output signal and provide low skew between the differential signals at the output pins. Selection circuits are used to select between single-ended and differential output.

摘要翻译： 电路和方法提供单端和差分信号。 单端驱动器用于例如降低引脚电容。 输出单元使用诸如分相器的反相电路从相同的输出信号导出差分信号，并在输出引脚之间的差分信号之间提供低偏差。 选择电路用于在单端和差分输出之间进行选择。