公开(公告)号：US20110227606A1

公开(公告)日：2011-09-22

申请号：US13149168

申请日：2011-05-31

申请人： Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Philip Pan

发明人： Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Philip Pan

IPC分类号： H03K19/0175 ,  H03K3/00

CPC分类号： H03K19/17744 ,  H03K19/0175 ,  H03K19/017509 ,  H03K19/017581 ,  H03K19/1774 ,  H03K19/17788

摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.

摘要翻译： 提供高速或低速灵活的输入和输出的方法和设备。 提供具有高速输入，高速输出，低速或中速输入以及低速或中速输出的输入和输出结构。 选择其中一个输入和输出电路，并取消选择其他电路。 高速输入和输出电路相对简单，在一个示例中，仅具有用于控制线输入的清除信号，并且能够与集成电路的核心内的低速电路接口。 低速或中速输入和输出电路比较灵活，例如具有预置，使能和清除作为控制线路输入，并且能够支持JTAG边界测试。 这些并行高速和低速电路是用户可选择的，使得输入输出结构根据应用的要求在速度和功能之间进行优化。

公开(公告)号：US20080186056A1

公开(公告)日：2008-08-07

申请号：US11830831

申请日：2007-07-30

申请人： Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Philip Pan

发明人： Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Philip Pan

IPC分类号： H03K19/0175

CPC分类号： H03K19/17744 ,  H03K19/0175 ,  H03K19/017509 ,  H03K19/017581 ,  H03K19/1774 ,  H03K19/17788

摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.

摘要翻译： 提供高速或低速灵活的输入和输出的方法和设备。 提供具有高速输入，高速输出，低速或中速输入以及低速或中速输出的输入和输出结构。 选择其中一个输入和输出电路，并取消选择其他电路。 高速输入和输出电路相当简单，在一个示例中，仅具有用于控制线路输入的清除信号，并且能够与集成电路的核心内的低速电路接口。 低速或中速输入和输出电路比较灵活，例如具有预置，使能和清除作为控制线路输入，并且能够支持JTAG边界测试。 这些并行高速和低速电路是用户可选择的，使得输入输出结构根据应用的要求在速度和功能之间进行优化。

公开(公告)号：US20100045349A1

公开(公告)日：2010-02-25

申请号：US12539606

申请日：2009-08-11

申请人： Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Philip Pan

发明人： Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Philip Pan

IPC分类号： H03K3/00

CPC分类号： H03K19/17744 ,  H03K19/0175 ,  H03K19/017509 ,  H03K19/017581 ,  H03K19/1774 ,  H03K19/17788

摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.

摘要翻译： 提供高速或低速灵活的输入和输出的方法和设备。 提供具有高速输入，高速输出，低速或中速输入以及低速或中速输出的输入和输出结构。 选择其中一个输入和输出电路，并取消选择其他电路。 高速输入和输出电路相对简单，在一个示例中，仅具有用于控制线输入的清除信号，并且能够与集成电路的核心内的低速电路接口。 低速或中速输入和输出电路比较灵活，例如具有预置，使能和清除作为控制线路输入，并且能够支持JTAG边界测试。 这些并行高速和低速电路是用户可选择的，使得输入输出结构根据应用的要求在速度和功能之间进行优化。

公开(公告)号：US08487665B2

公开(公告)日：2013-07-16

申请号：US13149168

申请日：2011-05-31

申请人： Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Philip Pan

发明人： Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Philip Pan

IPC分类号： H03B1/00

CPC分类号： H03K19/17744 ,  H03K19/0175 ,  H03K19/017509 ,  H03K19/017581 ,  H03K19/1774 ,  H03K19/17788

摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.

公开(公告)号：US07116135B2

公开(公告)日：2006-10-03

申请号：US10886015

申请日：2004-07-06

申请人： Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Philip Pan

发明人： Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Philip Pan

IPC分类号： H03B1/00

CPC分类号： H03K19/17744 ,  H03K19/0175 ,  H03K19/017509 ,  H03K19/017581 ,  H03K19/1774 ,  H03K19/17788

摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.

公开(公告)号：US06825698B2

公开(公告)日：2004-11-30

申请号：US10229342

申请日：2002-08-26

申请人： Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Philip Pan

发明人： Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Philip Pan

IPC分类号： H03B100

CPC分类号： H03K19/17744 ,  H03K19/0175 ,  H03K19/017509 ,  H03K19/017581 ,  H03K19/1774 ,  H03K19/17788

摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.

摘要翻译： 提供高速或低速灵活的输入和输出的方法和设备。 提供具有高速输入，高速输出，低速或中速输入以及低速或中速输出的输入和输出结构。 选择其中一个输入和输出电路，并取消选择其他电路。 高速输入和输出电路相当简单，在一个示例中，仅具有用于控制线路输入的清除信号，并且能够与集成电路的核心内的低速电路接口。 低速或中速输入和输出电路比较灵活，例如具有预置，使能和清除作为控制线路输入，并且能够支持JTAG边界测试。 这些并行高速和低速电路是用户可选择的，使得输入输出结构根据应用的要求在速度和功能之间进行优化。

公开(公告)号：US06433579B1

公开(公告)日：2002-08-13

申请号：US09863143

申请日：2001-05-22

申请人： Bonnie I. Wang ,  Chiakang Sung ,  Yan Chong ,  Philip Pan ,  Khai Nguyen ,  Joseph Huang ,  Xiaobao Wang ,  In Whan Kim ,  Gopinath Rangan

发明人： Bonnie I. Wang ,  Chiakang Sung ,  Yan Chong ,  Philip Pan ,  Khai Nguyen ,  Joseph Huang ,  Xiaobao Wang ,  In Whan Kim ,  Gopinath Rangan

IPC分类号： H03K19177

CPC分类号： H03K19/17744 ,  H03K19/018521 ,  H03K19/1778 ,  H03K19/17784 ,  H03K19/17792

摘要： A programmable logic device is equipped for various differential signaling schemes by providing a differential output buffer on the device that can be configured according to the needs of the particular differential signaling schemes that may be used. The buffer includes a differential output driver, an adjustable current limiting circuit between the supply voltage and the differential output driver, and an adjustable current limiting circuit between the differential output driver and ground. By selectively adjusting the two current limiting circuits, the output impedance and current, as well as the common mode output voltage and the differential output voltage can be controlled.

摘要翻译： 通过在设备上提供可根据可能使用的特定差分信令方案的需要进行配置的差分输出缓冲器，为各种差分信令方案配备了可编程逻辑器件。 缓冲器包括差分输出驱动器，电源电压和差分输出驱动器之间的可调节限流电路，以及差分输出驱动器和地之间的可调电流限制电路。 通过选择性地调节两个限流电路，可以控制输出阻抗和电流，以及共模输出电压和差分输出电压。

公开(公告)号：US06535031B1

公开(公告)日：2003-03-18

申请号：US10146438

申请日：2002-05-13

申请人： Khai Nguyen ,  Xiaobao Wang ,  In Whan Kim ,  Chiakang Sung ,  Richard G Cliff ,  Joseph Huang ,  Bonnie I Wang ,  Wayne Yeung

发明人： Khai Nguyen ,  Xiaobao Wang ,  In Whan Kim ,  Chiakang Sung ,  Richard G Cliff ,  Joseph Huang ,  Bonnie I Wang ,  Wayne Yeung

IPC分类号： H03K522

CPC分类号： H03K19/17744 ,  H03K19/018521 ,  H03K19/1778 ,  H03K19/17784

摘要： A programmable logic device is equipped for low voltage differential signaling (“LVDS”) by providing an LVDS input buffer and/or an LVDS output buffer on the device. I/O pins on the device that are used together in pairs for LVDS can alternatively be used individually for other types of signaling. The LVDS buffers are constructed to give good performance and to meet LVDS specifications despite variations due to temperature, manufacturing process inconsistency, and power supply changes.

公开(公告)号：US06384629B2

公开(公告)日：2002-05-07

申请号：US09738403

申请日：2000-12-15

申请人： Joseph Huang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen ,  Xiaobao Wang ,  Richard G. Cliff

发明人： Joseph Huang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen ,  Xiaobao Wang ,  Richard G. Cliff

IPC分类号： H01L2500

CPC分类号： H03K19/17736 ,  G01R31/318555 ,  G06F11/2273 ,  H03K19/17792

摘要： An improved interconnection between horizontal conductors and the input to logic elements. A signal regeneration circuit is provided in the path between the horizontal conductor and the logic element, thereby isolating and boosting the signal. This allows for faster switching operation. A path is provided allowing the selective routing of signals from the horizontal conductors to the vertical conductors, without passing through a logic element. Also, a path is provided to allow a horizontal conductors to be routed to any of a plurality of vertical conductors.

摘要翻译： 水平导体与逻辑元件输入之间的互连改善。 在水平导体和逻辑元件之间的路径中提供信号再生电路，从而隔离和升高信号。 这允许更快的切换操作。 提供路径，允许从水平导体到垂直导体的信号的选择性路由，而不通过逻辑元件。 而且，提供了一种路径，以允许水平导体被路由到多个垂直导体中的任何一个。

公开(公告)号：US09099999B1

公开(公告)日：2015-08-04

申请号：US13485768

申请日：2012-05-31

申请人： Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Tony Ngai ,  Zhe Li ,  Hong Shi

发明人： Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Tony Ngai ,  Zhe Li ,  Hong Shi

IPC分类号： H01L29/73 ,  H01L29/40 ,  H03K17/00 ,  H05K1/18 ,  H01L25/065 ,  H01L27/06

CPC分类号： H03K17/00 ,  H01L25/0652 ,  H01L25/0657 ,  H01L27/0688 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H05K1/144 ,  H05K1/181 ,  H05K2201/045 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  H01L2924/00

摘要： An integrated circuit in a multi-chip package is provided. The integrated circuit may include adjustable interface circuitry configured to interface with other off-chip components. In particular, the adjustable interface circuitry may include a microbump input-output buffer operable to drive signals off of the integrated circuit and operable to receive signals from other integrated circuits in the multi-chip package via a microbump. The microbump input-output buffer may include output buffers and input buffers. The output buffers may have programmable drive strengths and may each be selectively switched in and out of use depending on the desired application. Each output buffer may include a level shifter, a buffer circuit, and multiple inverter-like circuits each of which can be turned on or off to adjust the drive strength of that output buffer.

摘要翻译： 提供了一种多芯片封装中的集成电路。 该集成电路可以包括被配置为与其它片外部件接口的可调节接口电路。 特别地，可调接口电路可以包括微控制输入 - 输出缓冲器，其可操作用于驱动离开集成电路的信号，并且可操作以经由微型小型接收器从多芯片封装中的其他集成电路接收信号。 微控制输入 - 输出缓冲器可以包括输出缓冲器和输入缓冲器。 输出缓冲器可以具有可编程驱动强度，并且可以根据期望的应用选择性地切换和使用。 每个输出缓冲器可以包括电平移位器，缓冲电路和多个类似逆变器的电路，每个可以导通或关断以调整该输出缓冲器的驱动强度。