公开(公告)号：US08766711B2

公开(公告)日：2014-07-01

申请号：US13345112

申请日：2012-01-06

申请人： Yoshihiro Takemae

发明人： Yoshihiro Takemae

IPC分类号： H03K3/01

CPC分类号： H02M3/155 ,  H03K17/6877

摘要： A switching circuit device has a first transistor which has a drain coupled to a high-potential terminal, a source coupled to a low-potential power supply, and, a driving circuit, which outputs, to a gate of the first transistor in response to an input control signal, a pulse having a potential higher than a threshold voltage of the first transistor and a potential of the low-potential power supply, wherein the driving circuit has a first inverter including a second transistor provided between the gate and the source of the first transistor, wherein when the first transistor changes from on to off due to the pulse, the second transistor conducts and short-circuits the gate and the source of the first transistor.

摘要翻译： 开关电路器件具有第一晶体管，其具有耦合到高电位端子的漏极，耦合到低电位电源的源极和驱动电路，其响应于第一晶体管输出到第一晶体管的栅极 输入控制信号，具有高于第一晶体管的阈值电压的电位的脉冲和低电位电源的电位，其中驱动电路具有第一反相器，该第一反相器包括设置在栅极和源极之间的第二晶体管 第一晶体管，其中当第一晶体管由于脉冲而从接通变为截止时，第二晶体管导通并使第一晶体管的栅极和源极短路。

公开(公告)号：US20120091986A1

公开(公告)日：2012-04-19

申请号：US13181710

申请日：2011-07-13

申请人： Yoshihiro Takemae ,  Tsutomu Hosoda

发明人： Yoshihiro Takemae ,  Tsutomu Hosoda

IPC分类号： G05F3/08 ,  H01L27/088

CPC分类号： H01L27/088 ,  G05F3/08 ,  H01L21/8252 ,  H01L27/0605

摘要： A semiconductor device includes a first transistor including a GaN-based semiconductor stacked structure formed over a substrate, a first gate electrode having a plurality of first fingers over the semiconductor stacked structure, a plurality of first drain electrodes provided along the first fingers, and a plurality of first source electrodes provided along the first fingers; a second transistor including the semiconductor stacked structure, a second gate electrode having a plurality of second fingers over the semiconductor stacked structure, the second drain electrodes provided along the second fingers, and a plurality of second source electrodes provided along the second fingers; a drain pad provided over or under the first drain electrodes, and coupled to the first drain electrodes; a source pad provided over or under the second source electrodes, and coupled to the second source electrodes; and a common pad coupled to the first source electrodes and the second drain electrodes.

摘要翻译： 半导体器件包括：第一晶体管，包括在衬底上形成的GaN基半导体层叠结构，在半导体层叠结构上具有多个第一指状物的第一栅电极，沿着第一指状物设置的多个第一漏电极， 沿着第一指状物设置的多个第一源电极; 包括半导体层叠结构的第二晶体管，在半导体堆叠结构上具有多个第二指状物的第二栅极电极，沿着第二指状物设置的第二漏极电极以及沿着第二指状物设置的多个第二源极电极; 漏极焊盘，设置在所述第一漏电极之上或之下，并且耦合到所述第一漏电极; 源极焊盘，设置在所述第二源电极之上或之下，并且耦合到所述第二源电极; 以及耦合到第一源极和第二漏极的公共焊盘。

公开(公告)号：US5404328A

公开(公告)日：1995-04-04

申请号：US262352

申请日：1994-06-20

申请人： Yoshihiro Takemae

发明人： Yoshihiro Takemae

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C29/00 ,  H01L21/82 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC分类号： G11C29/789 ,  G11C16/0441 ,  G11C16/045 ,  G11C29/83 ,  G11C2216/10

摘要： A memory cell for storing data includes a first field effect transistor having a source receiving a first voltage, a floating gate, and a drain receiving data to be written into the memory cell and outputting the data, and a second field effect transistor having a source receiving a second voltage, a floating gate connected to the floating gate of the first field effect transistor, and a drain connected to the drain of the first field effect transistor. The second field effect transistor has a conduction type opposite to that of the first field effect transistor. The memory cell has a capacitor which has a first terminal receiving a select signal for identifying the memory cell, and a second terminal connected to the floating gates of the first and second field effect transistors. The data is stored in the floating gates of the first and second field effect transistors.

摘要翻译： 用于存储数据的存储单元包括：第一场效应晶体管，其具有接收第一电压的源极，浮置栅极和漏极接收要写入存储单元的数据并输出数据;以及第二场效应晶体管，具有源极 接收第二电压，连接到第一场效应晶体管的浮置栅极的浮动栅极和连接到第一场效应晶体管的漏极的漏极。 第二场效应晶体管具有与第一场效应晶体管相反的导通类型。 存储单元具有电容器，其具有接收用于识别存储单元的选择信号的第一端子和连接到第一和第二场效应晶体管的浮置栅极的第二端子。 数据存储在第一和第二场效应晶体管的浮置栅极中。

公开(公告)号：US5179536A

公开(公告)日：1993-01-12

申请号：US794705

申请日：1991-11-20

申请人： Yasushi Kasa ,  Yoshihiro Takemae ,  Masanori Nagasawa ,  Yuji Arayama ,  Akira Terui ,  Sunao Araki

发明人： Yasushi Kasa ,  Yoshihiro Takemae ,  Masanori Nagasawa ,  Yuji Arayama ,  Akira Terui ,  Sunao Araki

IPC分类号： G06F11/00 ,  G11C11/407 ,  G11C17/16 ,  G11C29/00

CPC分类号： G11C29/76 ,  G11C11/407 ,  G11C17/16 ,  G11C29/822 ,  G06F11/006

摘要： A semiconductor memory device comprises a first memory comprising memory cells for prestoring fixed data, a decoder for decoding an input address and for reading out a fixed data from the first memory based on a decoded input address, a second memory for storing a data identical to that prestored in a defective memory cell of the first memory, where the second memory comprising programmable non-volatile memory cells, a discriminating part including a third memory for storing a redundant address of each defective memory cell of the first memory for discriminating whether or not the input address coincides with the redundant address and for outputting a discrimination signal when the input address coincides with the redundant address, and a selecting part supplied with data read out from the first and second memories for normally outputting the data read out from the first memory and selectively outputting the data from the second memory when the discrimination signal is received from the discriminating part.

摘要翻译： 半导体存储器件包括：第一存储器，包括用于预先存储固定数据的存储器单元;解码器，用于解码输入地址，并且用于基于解码输入地址从第一存储器读出固定数据;第二存储器，用于存储与 预先存储在第一存储器的有缺陷的存储单元中，其中第二存储器包括可编程非易失性存储器单元，识别部分包括第三存储器，用于存储第一存储器的每个有缺陷的存储器单元的冗余地址，以区分是否 所述输入地址与所述冗余地址一致，并且当所述输入地址与所述冗余地址一致时输出鉴别信号，以及选择单元，提供从所述第一和第二存储器读出的数据，以正常地输出从所述第一存储器读出的数据 并且当从th接收到鉴别信号时，选择性地输出来自第二存储器的数据 识别部分。

公开(公告)号：US5025415A

公开(公告)日：1991-06-18

申请号：US412077

申请日：1989-09-25

申请人： Masaru Masuyama ,  Yoshihiro Takemae ,  Tetsuhiko Endoh ,  Hirosuke Komyoji ,  Ryuji Tanaka ,  Katsuhiko Itakura

发明人： Masaru Masuyama ,  Yoshihiro Takemae ,  Tetsuhiko Endoh ,  Hirosuke Komyoji ,  Ryuji Tanaka ,  Katsuhiko Itakura

IPC分类号： G06F12/00 ,  G06F12/04 ,  G06F12/06 ,  G06F13/16 ,  G06K7/00 ,  G06K19/07

CPC分类号： G06K19/07 ,  G06K7/0008

摘要： A memory card is used on a card write and/or read apparatus which has a data bus with an arbitrary bit width and writes and/or reads a datum to and/or from the memory card. The memory card comprises a data input/output terminal, a memory part having a data bus with a bit width of at least n bits for coupling to the data bus of the card write and/or read apparatus via the data input/output terminal, an address input terminal for receiving an address signal, a first input terminal for receiving a first chip select signal which selects a first byte, a second input terminal for receiving a second chip select signal which selects a second byte, and a decoder circuit for determining a bit width of the data bus of the memory part to be used for data communication between the card write and/or read apparatus to one of n bits and n/N bits based on the first and second chip select signals and one or a plurality of arbitrary bits of the address signal by supplying control signals to the memory part, where n, N and n/N are positive integers.

公开(公告)号：US4791610A

公开(公告)日：1988-12-13

申请号：US866507

申请日：1986-05-23

申请人： Yoshihiro Takemae

发明人： Yoshihiro Takemae

IPC分类号： G11C11/401 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C11/24 ,  G11C7/00 ,  G11C11/34

CPC分类号： H01L27/10829 ,  H01L27/10805

摘要： A semiconductor memory (DRAM) device comprises memory cells, each of which is composed of an FET and a capacitor. The FET has an SOI structure. The capacitor is composed of a dielectric layer as an insulating layer for the SOI structure, an upper capacitor electrode as a semiconductor layer for the SOI structure, and a lower capacitor electrode as a semiconductor substrate. The substrate is biased with a voltage at an intermediate level between a first storage voltage and a second storage voltage.

摘要翻译： 半导体存储器（DRAM）装置包括存储单元，每个存储单元由FET和电容器组成。 FET具有SOI结构。 电容器由作为SOI结构的绝缘层的电介质层，作为SOI结构的半导体层的上部电容电极和作为半导体基板的下部电容电极构成。 衬底被以第一存储电压和第二存储电压之间的中间电平的电压偏置。

公开(公告)号：US4649406A

公开(公告)日：1987-03-10

申请号：US619897

申请日：1984-06-12

申请人： Yoshihiro Takemae ,  Tomio Nakano ,  Kimiaki Sato

发明人： Yoshihiro Takemae ,  Tomio Nakano ,  Kimiaki Sato

IPC分类号： G11C11/4097 ,  H01L27/108 ,  G11C11/40

CPC分类号： G11C11/4097 ,  H01L27/10808

摘要： In a semiconductor memory device having stacked capacitor-type memory cells, the capacitor of each memory cell includes a base electrode, an insulating layer, and a counter electrode. The base electrode of each memory cell is partly superposed without contact on the base electrodes of other adjacent memory cells.

摘要翻译： 在具有层叠电容器型存储单元的半导体存储器件中，每个存储单元的电容器包括基极，绝缘层和对电极。 每个存储单元的基极部分重叠而不与其它相邻存储单元的基极接触。

公开(公告)号：US4602356A

公开(公告)日：1986-07-22

申请号：US445921

申请日：1982-12-01

申请人： Shigeki Nozaki ,  Yoshihiro Takemae ,  Seiji Enomoto

发明人： Shigeki Nozaki ,  Yoshihiro Takemae ,  Seiji Enomoto

IPC分类号： G11C11/41 ,  G11C7/00 ,  G11C8/00 ,  G11C8/18 ,  G11C11/407 ,  G11C11/408 ,  G11C11/413

CPC分类号： G11C8/18

摘要： A semiconductor memory device operates under a so-called address multiplex access method. A row part of the device is enabled by receiving a row address strobe (RAS) signal. A column part of the device is enabled by simultaneously receiving both a column address strobe (CAS) signal and a timing control signal supplied from the row part during its enable state. A column address buffer in the column part is enabled by simultaneously receiving both the CAS signal and a timing control signal. The timing control signal is produced from a circuit when it detects and holds the RAS signal.

摘要翻译： 半导体存储器件以所谓的地址复用存取方式工作。 器件的一部分通过接收行地址选通（＆upbar＆R）信号来使能。 器件的列部分通过在其使能状态期间同时接收列地址选通（＆upbar＆C）信号和从行部分提供的定时控制信号来启用。 列部分中的列地址缓冲器通过同时接收＆upbar＆C信号和定时控制信号而被使能。 定时控制信号从电路产生，当它检测并保持＆amp; R＆R信号。

公开(公告)号：US4443868A

公开(公告)日：1984-04-17

申请号：US318004

申请日：1981-11-04

申请人： Yoshihiro Takemae

发明人： Yoshihiro Takemae

IPC分类号： G11C11/419 ,  G11C11/401 ,  G11C11/409 ,  G11C11/4094 ,  G11C7/00

CPC分类号： G11C11/4094

摘要： Disclosed is a dynamic-type semiconductor memory device including a group of sense amplifiers, a plurality of pairs of bit lines extending from the sense amplifiers, and a plurality of dynamic-type memory cells connected to each bit line. Each pair of bit lines are short circuited and then precharged to a high potential level before a read operation. According to the present invention, a control line for activating the sense amplifiers is also used as a control line for short circuiting and precharging each pair of bit lines, resulting in a high degree of integration and a high short-circuiting speed.

摘要翻译： 公开了一种动态型半导体存储器件，其包括一组读出放大器，从读出放大器延伸的多对位线以及连接到每个位线的多个动态型存储单元。 每对位线短路，然后在读取操作之前预充电到高电位电平。 根据本发明，用于激活读出放大器的控制线也用作用于短路和预充电每对位线的控制线，导致高集成度和高​​短路速度。

公开(公告)号：US4443720A

公开(公告)日：1984-04-17

申请号：US215630

申请日：1980-12-12

申请人： Yoshihiro Takemae

发明人： Yoshihiro Takemae

IPC分类号： H03K5/02 ,  H03K19/017 ,  H03K19/096 ,  H03K5/01

CPC分类号： H03K5/023 ,  H03K19/01735 ,  H03K19/096

摘要： A bootstrap circuit in which a load MOS transistor and a drive MOS transistor are connected in series between a high potential source and a low potential source to form an inverter, a capacitor is connected to an output terminal of the inverter, and a circuit for charging the capacitor and a circuit for discharging the capacitor are connected to the capacitor, the circuit for discharging the capacitor being connected between said capacitor and the low potential source and containing a MOS transistor which is rendered conductive by a reset signal applied to its gate. The present invention involves another MOS transistor having its gate connected to the high potential source being inserted between the MOS transistor in the discharge circuit and the capacitor.

摘要翻译： 一种自举电路，其中负载MOS晶体管和驱动MOS晶体管串联连接在高电位源和低电位源之间以形成逆变器，电容器连接到逆变器的输出端子，并且充电电路 电容器和用于放电电容器的电路连接到电容器，用于将电容器放电的电路连接在所述电容器和低电位源之间，并且包含通过施加到其栅极的复位信号而导通的MOS晶体管。 本发明涉及另一个MOS晶体管，其栅极连接到高电位源，插入放电电路中的MOS晶体管和电容器之间。