公开(公告)号：US6140681A

公开(公告)日：2000-10-31

申请号：US292171

申请日：1999-04-15

申请人： Chen-Chung Hsu

发明人： Chen-Chung Hsu

IPC分类号： H01L27/02 ,  H01L29/72

CPC分类号： H01L27/0266

摘要： Provided is an electrostatic discharge protection circuit according to the invention. In a drain between a gate and a contact plug which is electrically coupled to an input line, a plurality of shallow trench isolation regions are alternately formed in a shape of lattices for extending a current flow path and efficiently increasing a dissipation length. Therefore, a current caused by an electrostatic discharge can be uniformly distributed, so that the inventive electrostatic discharge protection circuit can have an enhanced protective capability.

摘要翻译： 本发明提供一种静电放电保护电路。 在电耦合到输入线的栅极和接触插塞之间的漏极中，多个浅沟槽隔离区交替地形成为格子形状，用于延伸电流流动路径并有效地增加散热长度。 因此，可以均匀地分布由静电放电引起的电流，使得本发明的静电放电保护电路可以具有增强的保护能力。

公开(公告)号：US6066894A

公开(公告)日：2000-05-23

申请号：US16731

申请日：1998-01-30

申请人： Wataru Yokozeki

发明人： Wataru Yokozeki

IPC分类号： H01L21/225 ,  H01L21/28 ,  H01L21/336 ,  H01L23/485 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L29/6659 ,  H01L21/2257 ,  H01L21/28123 ,  H01L23/485 ,  H01L29/41783 ,  H01L2924/0002

摘要： A low-concentration impurity region and a high-concentration impurity region are formed respectively near the lower surface and the upper surface of an undoped polysilicon film by a first and second ion-implanations. A refractory metal film of tungsten or the like is formed on the polysilicon film. The impurities are thermally diffused to form shallow-junctions of source/drain having low-concentration impurities. Lead-out electrodes having a high-impurity concentration can be formed without impeding formation of the source and drain. The refractory metal film is converted into a silicide with the resistance at the interface between the polysilicon film and the silicide kept lowered.

公开(公告)号：US5962900A

公开(公告)日：1999-10-05

申请号：US909726

申请日：1997-08-12

申请人： Jih-Wen Chou ,  Jemmy Wen

发明人： Jih-Wen Chou ,  Jemmy Wen

IPC分类号： H01L21/8229 ,  H01L27/102 ,  H01L29/40 ,  H01L29/41

CPC分类号： H01L21/8229 ,  H01L27/1021 ,  Y10S257/926

摘要： A read-only memory (ROM) device of the type including an array of diode-based memory cells for permanent storage of binary-coded data. The ROM device is partitioned into a memory division and an output division. The memory cells are formed over an insulating layer in the memory division. The insulating layer separates the memory cells from the underlying substrate such that the leakage current that can otherwise occur therebetween can be prevented. Moreover, the coding process is performing by forming contact windows at selected locations rather than by performing ion-implantation as in conventional methods. The fabrication process is thus easy to perform. Since the memory cells are diode-based rather than MOSFET-based, the punch-through effect that usually occurs in MOSFET-based memory cells can be prevented. The diode-based structure also allows the packing density of the memory cells on the ROM device to be dependent on the line width of the polysilicon layers in the ROM device. The feature size of the ROM device is thus dependent on the capability of the photolithographic process. The integration of the ROM device is thus high. The output division includes a plurality of MOSFETs whose gates are coupled to the memory cells in such a manner that the binary data can be read out by detecting the currents in the source/drain regions of these MOSFETs.

摘要翻译： 一种只读存储器（ROM）器件，其类型包括用于永久存储二进制编码数据的基于二极管的存储器单元阵列。 ROM设备被划分为存储器部分和输出部分。 存储器单元形成在存储器分区中的绝缘层上。 绝缘层将存储器单元与下层衬底分离，从而可以防止其间发生的泄漏电流。 此外，编码过程是通过在所选位置形成接触窗而不是按照常规方法进行离子注入而进行的。 因此制造工艺容易执行。 由于存储器单元是基于二极管的而不是基于MOSFET的，所以可以防止通常发生在基于MOSFET的存储器单元中的穿透效应。 基于二极管的结构还允许ROM器件上的存储器单元的堆积密度取决于ROM器件中多晶硅层的线宽。 因此ROM器件的特征尺寸取决于光刻工艺的能力。 因此，ROM设备的集成度很高。 输出部分包括多个MOSFET，其栅极以这样的方式耦合到存储器单元，使得可以通过检测这些MOSFET的源极/漏极区域中的电流来读出二进制数据。

公开(公告)号：US5962342A

公开(公告)日：1999-10-05

申请号：US993870

申请日：1997-12-18

申请人： Andy Chuang ,  Tzung-Han Lee

发明人： Andy Chuang ,  Tzung-Han Lee

IPC分类号： H01L21/762 ,  H01L21/00

CPC分类号： H01L21/76232

摘要： An adjustable method for making trenches for a semiconductor IC device having eliminated top corners is disclosed. The adjustable method includes forming a masking layer on the surface of the silicon nitride layer covering the device substrate that has openings corresponding to the openings of the trenches formed. Dimension of the masking layer opening is relatively greater than the dimension of the opening of the corresponding trench. An anisotropic etching procedure is then performed against the portions of the device substrate exposed out of the coverage of the masking layer, and the anisotropic etching shapes the trench sidewalls into sloped ones having larger dimension at the opening than at the surface of the filling material inside the trenches. This eliminates the top corners at the edges of the trench opening, charge accumulation and consequent leakage current can thus be prevented.

摘要翻译： 公开了一种用于制造消除顶角的半导体IC器件的沟槽的可调节方法。 可调方法包括在覆盖器件基板的表面上形成掩模层，该掩模层具有与形成的沟槽的开口对应的开口。 掩模层开口的尺寸相对大于相应沟槽开口的尺寸。 然后针对暴露在掩模层的覆盖范围内的器件衬底的部分执行各向异性蚀刻过程，并且各向异性蚀刻将沟槽侧壁形成在开口处具有比在填充材料内部的表面处具有更大尺寸的倾斜的侧壁 壕沟 这消除了沟槽开口边缘的顶角，从而可以防止电荷累积和随之而来的泄漏电流。

公开(公告)号：US5910666A

公开(公告)日：1999-06-08

申请号：US928627

申请日：1997-09-12

申请人： Jemmy Wen

发明人： Jemmy Wen

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/417 ,  H01L29/78 ,  H01L29/76 ,  H01L29/80

CPC分类号： H01L29/66606 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/41766 ,  H01L29/7833 ,  H01L29/7834

摘要： A high-voltage MOS (metal-oxide semiconductor) device and a method for fabricating the same is provided. The high-voltage MOS device features the forming of trench-type source/drain structure in substitute of conventional highly doped structure formed by implantation. The improved structure allows the source/drain regions to occupy a small area for layout on the chip. In addition, the forming of the trench-type source/drain structure in N-wells allows an increased current path from the source/drain regions to drift regions, meaning that the conductive path for the current is not limited to only the junction between the source/drain regions and the drift regions as in conventional structures. Moreover, since the trench-type source/drain structure extends upwards from the inside of N-wells to above the surface of isolation layers, metal contact windows can be formed above the isolation layers, thus preventing the occurrence of leakage current.

摘要翻译： 提供高压MOS（金属氧化物半导体）器件及其制造方法。 高压MOS器件具有沟槽型源/漏结构的形成，代替了通过植入形成的常规高掺杂结构。 改进的结构允许源极/漏极区域占据小的面积用于芯片上的布局。 此外，在N阱中形成沟槽型源极/漏极结构允许从源/漏区到漂移区的电流路径增加，这意味着电流的导电路径不仅限于 源极/漏极区域和漂移区域。 此外，由于沟槽型源极/漏极结构从N阱的内部向上延伸到隔离层的表面之上，所以可以在隔离层上方形成金属接触窗口，从而防止漏电流的发生。

公开(公告)号：US5902752A

公开(公告)日：1999-05-11

申请号：US648618

申请日：1996-05-16

申请人： Shin-Wei Sun ,  Water Lur ,  Ming-Tzong Yang ,  Hong-Tsz Pan

发明人： Shin-Wei Sun ,  Water Lur ,  Ming-Tzong Yang ,  Hong-Tsz Pan

IPC分类号： H01L21/3105 ,  H01L21/762 ,  H01L23/528 ,  H01L27/02 ,  H01L21/283

CPC分类号： H01L27/0207 ,  H01L21/31053 ,  H01L21/76229 ,  H01L23/528 ,  H01L2924/0002

摘要： A method of designing an active layer mask with a dummy pattern by computer aided design (CAD) in shallow trench isolation using chemical mechanical polishing (CMP) to achieve global planarization. In this method, an original mask is provided with an active region including a diffusion area pattern, a polysilicon area pattern and a well area pattern. The diffusion area pattern and the polysilicon area pattern are expanded by an area of dimension a and the well area pattern is extended inward and outward to an area of dimension b. The expanded diffusion, polysilicon and well areas form a first pattern area. The first pattern area is subtracted from the whole region to obtain a second pattern area. A third pattern area is obtained by performing an AND operation on a dummy array pattern and the second pattern area. Expanding the third pattern area to an area of dimension c, a fourth pattern area is obtained. Finally an active layer mask with a dummy pattern is obtained by performing an OR operation on the fourth pattern area and the diffusion area pattern.

摘要翻译： 通过计算机辅助设计（CAD）在使用化学机械抛光（CMP）的浅沟槽隔离中设计具有虚拟图案的有源层掩模的方法来实现全局平面化。 在该方法中，原始掩模设置有包括扩散区域图案，多晶硅区域图案和阱区域图案的有源区域。 扩散区域图案和多晶硅区域图案通过尺寸a的面积扩大，并且阱区域图案向内和向外延伸到尺寸为b的区域。 扩展的扩散，多晶硅和阱区形成第一模式区域。 从整个区域中减去第一图案区域以获得第二图案区域。 通过对虚拟阵列图案和第二图案区域执行AND运算来获得第三图案区域。 将第三图案区域扩展到尺寸c的区域，获得第四图案区域。 最后，通过对第四图案区域和扩散区域图案执行OR运算来获得具有虚拟图案的有源层掩模。

公开(公告)号：US5895252A

公开(公告)日：1999-04-20

申请号：US552209

申请日：1995-11-02

申请人： Water Lur ,  Cheng Han Huang

发明人： Water Lur ,  Cheng Han Huang

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76213 ,  Y10S438/966

摘要： A method of forming a field oxide isolation region is described, in which a masking layer is formed over a silicon substrate. The masking layer is patterned to form an opening for the field oxide isolation region, whereby the remainder of the masking layer forms an implant mask. A conductivity-imparting dopant is implanted through the opening into the silicon substrate. Oxygen is implanted through the opening into the silicon substrate in multiple implantation steps. The implant mask is removed. The field oxide isolation region is formed in and on the silicon substrate, by annealing in a non-oxygen ambient. Alternately, the field oxide isolation region is formed by annealing in oxygen, simultaneously forming a gate oxide in the region between the field oxide isolation regions.

摘要翻译： 描述了形成场氧化物隔离区域的方法，其中在硅衬底上形成掩模层。 图案化掩模层以形成用于场氧化物隔离区的开口，由此掩模层的其余部分形成植入掩模。 通过开口将导电性赋予掺杂剂注入到硅衬底中。 在多个注入步骤中，氧气通过开口注入硅衬底。 移除植入物掩模。 通过在非氧环境中退火，在硅衬底中和硅衬底上形成场氧化物隔离区。 或者，通过在氧中退火而形成场氧化物隔离区，同时在场氧化物隔离区之间的区域中形成栅极氧化物。

公开(公告)号：US5894155A

公开(公告)日：1999-04-13

申请号：US947915

申请日：1997-10-09

申请人： Sheng-Hsing Yang

发明人： Sheng-Hsing Yang

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/13

CPC分类号： H01L29/7833 ,  H01L21/823814 ,  H01L27/0927 ,  H01L29/0638 ,  H01L29/1087 ,  Y10S148/126

摘要： A semiconductor is made on a silicon substrate containing an impurity of a predetermined polarity having formed therein a well containing an impurity of an opposite polarity to a region in the silicon is provided. The method comprises forming a first masking layer on the surface of the substrate, providing openings in the masking layer and implanting dopant ions of a first polarity into the surface of the substrate in a set of first implant regions in the well on either side of a first central region in the well and in a set of second implant regions adjacent to the well on either side of a second central region adjacent to the well, formation of insulating structures over the first and second regions, forming gate oxide layers above the first and second central regions, forming a second masking layer on the surface of the substrate, providing openings in the masking layer and implanting dopant ions of a second polarity into the surface of the substrate in a set of second implant regions in the well on either side of a first central region in the well and in a set of fourth implant regions adjacent to the well on either side of a second central region adjacent to the well, and formation of conductive gate structures over the gate oxide layers.

摘要翻译： 在硅衬底上形成半导体，该硅衬底上形成有预定极性的杂质，其中形成有含有与硅中的区域相反极性的杂质的阱。 该方法包括在衬底的表面上形成第一掩模层，在掩模层中提供开口并将第一极性的掺杂剂离子注入到衬底的表面中的一组第一注入区域 在井中的第一中心区域和与井相邻的第二中心区域的两侧邻近井的一组第二注入区域，在第一和第二区域上形成绝缘结构，在第一和第二区域上方形成栅极氧化物层， 第二中心区域，在衬底的表面上形成第二掩模层，在掩模层中提供开口，并将第二极性的掺杂剂离子注入衬底的表面， 井中的第一中心区域和邻近井的第二中心区域的两侧邻近孔的一组第四植入区域，以及导管 栅极氧化物层上的栅极结构。

公开(公告)号：US5891772A

公开(公告)日：1999-04-06

申请号：US859207

申请日：1997-05-20

申请人： Chen-Chung Hsu

发明人： Chen-Chung Hsu

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/87

摘要： A structure and manufacturing method for DRAM capacitors includes providing a semiconductor substrate with a MOS transistor having a gate and source/drain regions formed thereon. A first insulating layer covers the semiconductor substrate. A multi-layered stack, with at least one pair of an alternately deposited second insulating layer followed by a third insulating layer, is formed above the first insulating layer. An opening is formed through the multi-layered structure and the first insulating layer exposing the source/drain region. Then, a plurality of trenches are formed on the sidewalls of the opening. A second conducting layer is formed over the exposed surfaces of the aforementioned layers. A pattern is defined on the second conducting layer so as to form a lower electrode structure. A dielectric layer is formed over the lower electrode layer. A third conducting layer is formed over the dielectric layer, and a pattern is defined on the third conducting layer to form the upper electrode structure.

摘要翻译： DRAM电容器的结构和制造方法包括为半导体衬底提供其上形成有栅极和源极/漏极区域的MOS晶体管。 第一绝缘层覆盖半导体衬底。 在第一绝缘层的上方形成有至少一对交替沉积的第二绝缘层和第三绝缘层的多层叠层。 通过多层结构形成开口，并且第一绝缘层暴露源/漏区。 然后，在开口的侧壁上形成多个沟槽。 在上述层的暴露表面上形成第二导电层。 在第二导电层上形成图案，形成下部电极结构。 在下电极层上形成电介质层。 在电介质层上形成第三导电层，并且在第三导电层上形成图案以形成上电极结构。

公开(公告)号：US5874353A

公开(公告)日：1999-02-23

申请号：US927321

申请日：1997-09-11

申请人： Tony Lin ,  Water Lur ,  Shih-Wei Sun

发明人： Tony Lin ,  Water Lur ,  Shih-Wei Sun

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/28061 ,  H01L29/4925 ,  H01L29/4941

摘要： A method of forming self-aligned silicide devices which includes providing a silicon substrate having shallow trench isolation regions for defining a device area formed therein; then, forming sequentially a gate oxide layer, a polysilicon layer, a first titanium nitride layer, a titanium silicide layer, a second titanium nitride layer and a silicon nitride layer over the substrate. After a gate electrode is etched out from the above layers, a titanium layer is deposited over the device, and then a self-aligned titanium silicide layer is formed using a heating process. The use of a titanium silicide layer having protective top and bottom titanium nitride layers, compared with a single tungsten silicide layer in a conventional method, provides for a self-aligned silicide device having a rather low gate resistance; being free from narrow width effect of a titanium self-aligned silicide layer; is applicable to self-aligned contact window processes, and avoids the cross-diffusion of doped ions in the polysilicon layer of a dual gate electrode having a tungsten polycide layer.

摘要翻译： 一种形成自对准硅化物器件的方法，其包括提供具有浅沟槽隔离区域的硅衬底，用于限定其中形成的器件区域; 然后在衬底上依次形成栅氧化层，多晶硅层，第一氮化钛层，硅化钛层，第二氮化钛层和氮化硅层。 在从上述层蚀刻出栅电极之后，在器件上沉积钛层，然后使用加热工艺形成自对准硅化钛层。 与常规方法中的单个硅化钨层相比，使用具有保护性顶部和底部氮化钛层的硅化钛层提供具有相当低的栅极电阻的自对准硅化物器件; 没有钛自对准硅化物层的窄宽度效应; 适用于自对准接触窗工艺，并避免掺杂离子在具有钨多硅化物层的双栅电极的多晶硅层中的交叉扩散。