公开(公告)号：US06320254B1

公开(公告)日：2001-11-20

申请号：US09289773

申请日：1999-04-08

申请人： Fu-Tai Liou ,  Andy Chuang

发明人： Fu-Tai Liou ,  Andy Chuang

IPC分类号： H01L2348

CPC分类号： H05K3/325 ,  H01L23/13 ,  H01L23/3157 ,  H01L23/3171 ,  H01L23/32 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/81 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05567 ,  H01L2224/13099 ,  H01L2224/16237 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/48799 ,  H01L2224/81192 ,  H01L2224/81898 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A plug structure capable of directly coupling to a packageless bonding pad without having to go through a third conductive medium. The plug structure includes several plugs on a base substrate, such as a printed circuit board or a carrier. A solder is disposed on the plug surface in which the plug can be a cylinder or mushroom-like shape and the solder can be a film or a ball.

摘要翻译： 一种能够直接耦合到无封装焊盘而不必经过第三导电介质的插头结构。 插头结构在基底基板上包括几个插头，例如印刷电路板或载体。 焊料被布置在插头表面上，其中插头可以是气缸或蘑菇状形状，并且焊料可以是膜或球。

公开(公告)号：US5936279A

公开(公告)日：1999-08-10

申请号：US954410

申请日：1997-10-20

申请人： Andy Chuang

发明人： Andy Chuang

IPC分类号： H01L21/60 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L21/76897

摘要： A gate oxide layer, a polysilicon layer are patterned on a substrate. Then, a thermal oxidation is carried out to form the first silicon dioxide layer on the surface of the polysilicon layer. Then, a first silicon nitride layer is patterned on the first silicon dioxide layer, over the top of the polysilicon layer. Then, a second silicon nitride layer is formed on the first silicon dioxide layer and the first silicon nitride layer. Next, a second silicon dioxide layer is formed on the second silicon nitride layer. Then, an etching technique is used to form the side-wall spacers. The side-wall spacers composed of silicon nitride layer and silicon dioxide layer. A dielectric layer is formed on the cap layer, side-wall spacers and silicon dioxide layer. An etch with high selectivity is used to etch the dielectric layer to create a contact hole.

摘要翻译： 栅极氧化层，多晶硅层在衬底上图案化。 然后，进行热氧化以在多晶硅层的表面上形成第一二氧化硅层。 然后，在第一二氧化硅层上，在多晶硅层的顶部上形成第一氮化硅层。 然后，在第一二氧化硅层和第一氮化硅层上形成第二氮化硅层。 接着，在第二氮化硅层上形成第二二氧化硅层。 然后，使用蚀刻技术来形成侧壁间隔物。 由氮化硅层和二氧化硅层组成的侧壁间隔物。 在盖层，侧壁间隔物和二氧化硅层上形成介电层。 使用具有高选择性的蚀刻来蚀刻介电层以产生接触孔。

公开(公告)号：US6093609A

公开(公告)日：2000-07-25

申请号：US193975

申请日：1998-11-18

申请人： Andy Chuang

发明人： Andy Chuang

IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/336

CPC分类号： H01L21/28518 ,  H01L21/76895

摘要： A method has a feature that one side of the spacers surrounding a gate of a MOS transistor is removed and another side of the spacers is exposed. By the method of this invention, the gate, the source and the pick-up region of a well are electrically connected by a plug through a silicide layer covering them. Furthermore, the pick-up region is adjacent to the source such that the effective surface area can be reduced and the process has a higher error tolerance.

摘要翻译： 一种方法具有以下特征：消除了MOS晶体管的栅极周围的间隔物的一侧，并且间隔物的另一侧被暴露。 通过本发明的方法，阱的栅极，源极和拾取区域通过插塞通过覆盖它们的硅化物层电连接。 此外，拾取区域与源极相邻，使得有效表面积可以减小，并且该工艺具有较高的误差容限。

公开(公告)号：US6054362A

公开(公告)日：2000-04-25

申请号：US138756

申请日：1998-08-24

申请人： Andy Chuang

发明人： Andy Chuang

IPC分类号： H01L21/3105 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76229 ,  H01L21/31053 ,  Y10S438/959

摘要： A method of patterning a dummy layer is provided using the dark/clear ratio. First, the area of devices and the area of relevant devices are defined. The relevant devices are usually positioned around the devices. The devices, the relevant devices, and other regions are united according to the design rules to form a non-dummy pattern region. Then a dummy pattern region is defined. There are many dummy bulks in the dummy pattern region. Next, a known dark/clear ratio of the non-dummy pattern region is provided. A density of the dummy patterns is obtained from the known dark/clear ratio, the length of the dummy bulk, the width of the dummy bulk and a equation. The equation is as follows: the known dark/clear ratio=(the length-the parameter)(the width-the parameter)/[the length.times.the width-(the length-the parameter)(the width-the parameter)]. After obtaining the parameter, each dummy bulk is divided into two regions including a clear region and a dark region. A dummy layer is formed in the dark region of the dummy bulk.

摘要翻译： 使用暗/透明比提供图案化虚拟层的方法。 首先，定义设备的面积和相关设备的面积。 相关设备通常位于设备周围。 根据设计规则将设备，相关设备和其他区域联合成一个非虚拟模式区域。 然后定义虚拟图案区域。 虚拟图案区域中有许多虚拟块。 接下来，提供非虚拟图案区域的已知暗/清除比率。 从已知的暗/清除比，虚拟体的长度，虚拟体的宽度和等式获得虚拟图案的密度。 公式如下：已知的暗/清除率=（参数的长度）（宽度 - 参数）/ [宽度 - （参数的长度）（宽度 - 参数）]。 在获得参数后，将每个虚拟块分为包括清晰区域和暗区域的两个区域。 虚拟体的暗区形成虚拟层。

公开(公告)号：US06180515B2

公开(公告)日：2001-01-30

申请号：US09090726

申请日：1998-06-04

申请人： Andy Chuang

发明人： Andy Chuang

IPC分类号： H01L214763

CPC分类号： H01L21/76897

摘要： A gate oxide layer, a polysilicon layer are patterned on a substrate. Then, a thermal oxidation is carried out to form the first silicon dioxide layer on the surface of the polysilicon layer. Then, a first silicon nitride layer is patterned on the first silicon dioxide layer, over the top of the polysilicon layer. Then, a second silicon nitride layer is formed on the first silicon dioxide layer and the first silicon nitride layer. Next, a second silicon dioxide layer is formed on the second silicon nitride layer. Then, an etching technique is used to form the side-wall spacers. The side-wall spacers composed of silicon nitride layer and silicon dioxide layer. A dielectric layer is formed on the cap layer, side-wall spacers and silicon dioxide layer. An etch with high selectivity is used to etch the dielectric layer to create a contact hole.

摘要翻译： 栅极氧化层，多晶硅层在衬底上图案化。 然后，进行热氧化以在多晶硅层的表面上形成第一二氧化硅层。 然后，在第一二氧化硅层上，在多晶硅层的顶部上形成第一氮化硅层。 然后，在第一二氧化硅层和第一氮化硅层上形成第二氮化硅层。 接着，在第二氮化硅层上形成第二二氧化硅层。 然后，使用蚀刻技术来形成侧壁间隔物。 由氮化硅层和二氧化硅层组成的侧壁间隔物。 在盖层，侧壁间隔物和二氧化硅层上形成介电层。 使用具有高选择性的蚀刻来蚀刻介电层以产生接触孔。

公开(公告)号：US6008080A

公开(公告)日：1999-12-28

申请号：US975488

申请日：1997-11-21

申请人： Andy Chuang ,  Tzong-Shien Wu ,  Sun-Chieh Chien

发明人： Andy Chuang ,  Tzong-Shien Wu ,  Sun-Chieh Chien

IPC分类号： H01L21/8244 ,  H01L27/02 ,  H01L27/11 ,  H01L21/70

CPC分类号： H01L27/11 ,  H01L27/0266 ,  H01L27/1104 ,  H01L27/1108

摘要： An SRAM is formed having the six transistor cell. The pull down transistors are formed so that no arsenic is implanted into the drains of the pull down transistors so that the drains of the pull down transistors are doped only by phosphorus implantation. The sources of the pull down transistors are doped with an LDD configuration of phosphorus ions and then a further implantation of arsenic ions is performed. This can conveniently be accomplished by providing an opening in the mask used to implant impurities into the source/drain regions of the ESD protection circuit.

摘要翻译： 形成具有六个晶体管单元的SRAM。 形成下拉晶体管，使得没有砷被注入到下拉晶体管的漏极中，使得下拉晶体管的漏极仅通过磷注入​​掺杂。 下拉晶体管的源极掺杂有磷离子的LDD配置，然后进一步注入砷离子。 这可以通过在用于将杂质注入到ESD保护电路的源极/漏极区域中的掩模中提供开口来方便地实现。

公开(公告)号：US5962342A

公开(公告)日：1999-10-05

申请号：US993870

申请日：1997-12-18

申请人： Andy Chuang ,  Tzung-Han Lee

发明人： Andy Chuang ,  Tzung-Han Lee

IPC分类号： H01L21/762 ,  H01L21/00

CPC分类号： H01L21/76232

摘要： An adjustable method for making trenches for a semiconductor IC device having eliminated top corners is disclosed. The adjustable method includes forming a masking layer on the surface of the silicon nitride layer covering the device substrate that has openings corresponding to the openings of the trenches formed. Dimension of the masking layer opening is relatively greater than the dimension of the opening of the corresponding trench. An anisotropic etching procedure is then performed against the portions of the device substrate exposed out of the coverage of the masking layer, and the anisotropic etching shapes the trench sidewalls into sloped ones having larger dimension at the opening than at the surface of the filling material inside the trenches. This eliminates the top corners at the edges of the trench opening, charge accumulation and consequent leakage current can thus be prevented.

摘要翻译： 公开了一种用于制造消除顶角的半导体IC器件的沟槽的可调节方法。 可调方法包括在覆盖器件基板的表面上形成掩模层，该掩模层具有与形成的沟槽的开口对应的开口。 掩模层开口的尺寸相对大于相应沟槽开口的尺寸。 然后针对暴露在掩模层的覆盖范围内的器件衬底的部分执行各向异性蚀刻过程，并且各向异性蚀刻将沟槽侧壁形成在开口处具有比在填充材料内部的表面处具有更大尺寸的倾斜的侧壁 壕沟 这消除了沟槽开口边缘的顶角，从而可以防止电荷累积和随之而来的泄漏电流。

公开(公告)号：US06153479A

公开(公告)日：2000-11-28

申请号：US74959

申请日：1998-05-07

申请人： Wei-Wu Liao ,  Andy Chuang ,  Chien-Li Kuo

发明人： Wei-Wu Liao ,  Andy Chuang ,  Chien-Li Kuo

IPC分类号： H01L21/762 ,  H01L21/336 ,  H01L21/461 ,  H01L21/76

CPC分类号： H01L21/76224

摘要： A method of fabricating shallow trench isolation structures. A substrate is provided and a masking layer and an oxide layer are formed respectively on the substrate. The masking layer, the oxide layer and the substrate are defined and an opening is formed within the substrate. A portion of masking layer and the oxide layer are removed and an insulating material is later formed to fill with the opening. The masking layer is removed and the shallow trench isolation structure of this invention is therefore achieved.

摘要翻译： 一种制造浅沟槽隔离结构的方法。 提供基板，并且在基板上分别形成掩模层和氧化物层。 限定掩模层，氧化物层和衬底，并在衬底内形成开口。 去除一部分掩模层和氧化物层，然后形成绝缘材料以填充开口。 去除掩模层，从而实现本发明的浅沟槽隔离结构。

公开(公告)号：US5814553A

公开(公告)日：1998-09-29

申请号：US647410

申请日：1996-05-09

申请人： Andy Chuang ,  Tzong-Shien Wu

发明人： Andy Chuang ,  Tzong-Shien Wu

IPC分类号： H01L21/311 ,  H01L21/60 ,  H01L21/3205

CPC分类号： H01L21/76897 ,  H01L21/31116 ,  Y10S438/97

摘要： The process of the present invention has numerous advantages over the prior art. The silicon nitride side-wall spacers permit a small contact hole thus miniaturizing the cell beyond lithographic limits. The side-wall spacers composed of silicon nitride and silicon dioxide avoid to expose the polysilicon when the contact window is formed by etching step. Moreover, the highly selective etching process improve the accuracy of the contact window.

摘要翻译： 本发明的方法与现有技术相比具有许多优点。 氮化硅侧壁间隔物允许小的接触孔，从而使电池小于光刻极限。 当通过蚀刻步骤形成接触窗口时，由氮化硅和二氧化硅组成的侧壁间隔物避免暴露多晶硅。 此外，高选择性蚀刻工艺提高了接触窗的精度。