公开(公告)号：US5902752A

公开(公告)日：1999-05-11

申请号：US648618

申请日：1996-05-16

申请人： Shin-Wei Sun ,  Water Lur ,  Ming-Tzong Yang ,  Hong-Tsz Pan

发明人： Shin-Wei Sun ,  Water Lur ,  Ming-Tzong Yang ,  Hong-Tsz Pan

IPC分类号： H01L21/3105 ,  H01L21/762 ,  H01L23/528 ,  H01L27/02 ,  H01L21/283

CPC分类号： H01L27/0207 ,  H01L21/31053 ,  H01L21/76229 ,  H01L23/528 ,  H01L2924/0002

摘要： A method of designing an active layer mask with a dummy pattern by computer aided design (CAD) in shallow trench isolation using chemical mechanical polishing (CMP) to achieve global planarization. In this method, an original mask is provided with an active region including a diffusion area pattern, a polysilicon area pattern and a well area pattern. The diffusion area pattern and the polysilicon area pattern are expanded by an area of dimension a and the well area pattern is extended inward and outward to an area of dimension b. The expanded diffusion, polysilicon and well areas form a first pattern area. The first pattern area is subtracted from the whole region to obtain a second pattern area. A third pattern area is obtained by performing an AND operation on a dummy array pattern and the second pattern area. Expanding the third pattern area to an area of dimension c, a fourth pattern area is obtained. Finally an active layer mask with a dummy pattern is obtained by performing an OR operation on the fourth pattern area and the diffusion area pattern.

摘要翻译： 通过计算机辅助设计（CAD）在使用化学机械抛光（CMP）的浅沟槽隔离中设计具有虚拟图案的有源层掩模的方法来实现全局平面化。 在该方法中，原始掩模设置有包括扩散区域图案，多晶硅区域图案和阱区域图案的有源区域。 扩散区域图案和多晶硅区域图案通过尺寸a的面积扩大，并且阱区域图案向内和向外延伸到尺寸为b的区域。 扩展的扩散，多晶硅和阱区形成第一模式区域。 从整个区域中减去第一图案区域以获得第二图案区域。 通过对虚拟阵列图案和第二图案区域执行AND运算来获得第三图案区域。 将第三图案区域扩展到尺寸c的区域，获得第四图案区域。 最后，通过对第四图案区域和扩散区域图案执行OR运算来获得具有虚拟图案的有源层掩模。

公开(公告)号：US08062536B2

公开(公告)日：2011-11-22

申请号：US12729234

申请日：2010-03-22

申请人： Chih-Chien Liu ,  Ta-Shan Tseng ,  Wen-Bin Shieh ,  Juan-Yuan Wu ,  Water Lur ,  Shih-Wei Sun

发明人： Chih-Chien Liu ,  Ta-Shan Tseng ,  Wen-Bin Shieh ,  Juan-Yuan Wu ,  Water Lur ,  Shih-Wei Sun

IPC分类号： H01L21/467 ,  H01L21/32 ,  H01L21/308 ,  H01L21/762

CPC分类号： H01L21/02112 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/0276 ,  H01L21/31612 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76838

摘要： A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.

摘要翻译： 在形成半导体器件时，将介电材料沉积在布线之间的间隙中的方法包括形成盖层并形成间隙，沉积高密度等离子体化学气相沉积（HDPCVD）电介质材料。 第一和第二抗反射涂层可以形成在布线层上，第一和第二抗反射涂层由不同的材料制成。 防反射涂层和布线层都被蚀刻通过以形成由间隙分开的布线。 可以使用高密度等离子体化学气相沉积来填充布线之间的间隙。

公开(公告)号：US07378740B2

公开(公告)日：2008-05-27

申请号：US11196038

申请日：2005-08-02

申请人： Tri-Rung Yew ,  Yimin Huang ,  Water Lur ,  Shih-Wei Sun

发明人： Tri-Rung Yew ,  Yimin Huang ,  Water Lur ,  Shih-Wei Sun

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/7681 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An improved dual damascene structure is provided for use in the wiring-line structures of multi-level interconnects in integrated circuit. In this dual damascene structure, low-K (low dielectric constant) dielectric materials are used to form both the di-electric layers and the etch-stop layers between the metal interconnects in the IC device. With this feature, the dual damascene structure can prevent high parasite capacitance to occur therein that would otherwise cause large RC delay to the signals being transmitted through the metal interconnects and thus degrade the performance of the IC device. With the dual damascene structure, such parasite capacitance can be reduced, thus assuring the performance of the IC device.

摘要翻译： 提供了一种改进的双镶嵌结构，用于集成电路中多级互连的布线结构。 在这种双镶嵌结构中，使用低K（低介电常数）介电材料来形成IC器件中的金属互连之间的二电层和蚀刻停止层。 利用该特征，双镶嵌结构可以防止在其中发生高的寄生电容，否则会对通过金属互连传输的信号造成较大的RC延迟，从而降低IC器件的性能。 利用双镶嵌结构，可以减少这种寄生电容，从而确保IC器件的性能。

公开(公告)号：US20070076339A1

公开(公告)日：2007-04-05

申请号：US11561790

申请日：2006-11-20

申请人： Water Lur ,  David Lee ,  Kuang-Chih Wang ,  Ming-Sheng Yang

发明人： Water Lur ,  David Lee ,  Kuang-Chih Wang ,  Ming-Sheng Yang

IPC分类号： H02H9/00

CPC分类号： H01L21/7682 ,  H01L21/76807

摘要： An air gap structure substantially reduces undesired capacitance between adjacent interconnects, metal lines or other features in an integrated circuit device. The air gap extends above, and may also additionally extend below, the interconnects desired to be isolated thus minimizing fringing fields between the lines. The integrated air gap structure can be utilized in conjunction with a tungsten plug process. Also, multiple levels of the integrated air gap structure can be fabricated to accommodate multiple metal levels while always ensuring that physical dielectric layer support is provided to the device structure underlying the interconnects.

摘要翻译： 气隙结构基本上减少了集成电路器件中相邻互连，金属线或其他特征之间的不需要的电容。 空气间隙在期望被隔离的互连之上延伸并且还可以另外延伸，从而最小化线之间的边缘场。 集成气隙结构可以与钨丝塞过程一起使用。 此外，可以制造多个级别的集成气隙结构以适应多个金属水平，同时始终确保将物理介电层支撑件提供给互连下面的器件结构。

公开(公告)号：US20060099824A1

公开(公告)日：2006-05-11

申请号：US11315904

申请日：2005-12-22

申请人： Chih-Chien Liu ,  Ta-Shan Tseng ,  W.B. Shieh ,  J.Y. Wu ,  Water Lur ,  Shih-Wei Sun

发明人： Chih-Chien Liu ,  Ta-Shan Tseng ,  W.B. Shieh ,  J.Y. Wu ,  Water Lur ,  Shih-Wei Sun

IPC分类号： H01L21/31

CPC分类号： H01L21/02112 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/0276 ,  H01L21/31612 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76838

摘要： A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.

公开(公告)号：US20060009005A1

公开(公告)日：2006-01-12

申请号：US10984045

申请日：2004-11-09

申请人： Coming Chen ,  Juan-Yuan Wu ,  Water Lur

发明人： Coming Chen ,  Juan-Yuan Wu ,  Water Lur

IPC分类号： H01L21/76 ,  H01L21/302

CPC分类号： H01L21/31144 ,  H01L21/31053 ,  H01L21/31056 ,  H01L21/76229 ,  Y10S438/942

摘要： A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relatively large active regions and a number of relatively small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is first formed. A number of shallow trenches are formed between the active regions. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial reverse active mask has an opening at a central part of each relatively large active region. The opening exposes a portion of the oxide layer. The opening has at least a dummy pattern. The oxide layer on the central part of each large active region is removed to expose the silicon nitride layer. The partial reverse active mask is removed. The oxide layer is planarized to expose the silicon nitride layer.

摘要翻译： 公开了用于形成浅沟槽隔离的化学机械抛光的方法。 提供具有多个有源区的基板，包括多个相对较大的有源区和多个相对小的有源区。 该方法包括以下步骤。 首先形成衬底上的氮化硅层。 在活性区域之间形成多个浅沟槽。 在衬底上形成氧化物层，使得浅沟槽被氧化物层填充。 在氧化物层上形成部分反向有源掩模。 部分反向有源掩模在每个相对大的有效区域的中心部分具有开口。 开口暴露氧化物层的一部分。 开口至少有一个虚拟图案。 去除每个大的有源区的中心部分的氧化物层，以露出氮化硅层。 去除部分反向主动掩模。 将氧化物层平坦化以暴露氮化硅层。

公开(公告)号：US06810511B2

公开(公告)日：2004-10-26

申请号：US10284683

申请日：2002-10-30

申请人： Coming Chen ,  Juan-Yuan Wu ,  Water Lur

发明人： Coming Chen ,  Juan-Yuan Wu ,  Water Lur

IPC分类号： G06F1750

CPC分类号： H01L21/31053 ,  H01L21/76229 ,  H01L23/528 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of designing an active region pattern with a shifted dummy pattern, wherein an integrated circuit having an original active region pattern thereon is provided. The original active region pattern is expanded with a first parameter of line width to obtain a first pattern. By subtracting the first pattern, a second pattern is obtained. A dummy pattern which comprises an array of a plurality of elements is provided. By shifting the elements, a shifted dummy pattern is obtained. The second pattern and the shifted dummy pattern are combined, so that an overlapped region thereof is extracted as a combined dummy pattern. The combined dummy pattern is expanded with a second parameter of line width, so that a resultant dummy pattern is obtained. The resultant dummy pattern is added to the first pattern, so that the active region pattern with a shifted dummy pattern is obtained.

摘要翻译： 一种设计具有偏移的虚设图案的有源区域图案的方法，其中提供其上具有原始有源区域图案的集成电路。 原始活动区域图案用线宽的第一参数展开以获得第一图案。 通过减去第一图案，获得第二图案。 提供了包括多个元件的阵列的虚拟图案。 通过移动元件，获得移动的虚拟图案。 第二图案和移位的虚拟图案被组合，使得其重叠区域被提取为组合的虚拟图案。 组合的虚拟图案用线宽的第二参数扩展，从而获得合成的虚拟图案。 将所得到的虚拟图案添加到第一图案，从而获得具有偏移的虚设图案的有源区域图案。

公开(公告)号：US06790742B2

公开(公告)日：2004-09-14

申请号：US10293243

申请日：2002-11-13

申请人： Ming-Sheng Yang ,  Juan-Yuan Wu ,  Water Lur

发明人： Ming-Sheng Yang ,  Juan-Yuan Wu ,  Water Lur

IPC分类号： H01L2176

CPC分类号： H01L21/76229

摘要： A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relatively large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is formed. A number of shallow trenches are formed between the active regions one or more of which may constitute an alignment mark. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial reverse active mask exposes a portion of the oxide layer over the large active area and over the alignment mark. The oxide layer of each large active region and the alignment mark is removed. The partial reverse active mask is removed. The oxide layer is planarized.

摘要翻译： 公开了用于形成浅沟槽隔离的化学机械抛光的方法。 提供了具有多个有效区域的基板，包括多个相对较大的有源区域和多个相对小的有源区域。 该方法包括以下步骤。 形成衬底上的氮化硅层。 在有源区域之间形成多个浅沟槽，其中一个或多个可以构成对准标记。 在衬底上形成氧化物层，使得浅沟槽被氧化物层填充。 在氧化物层上形成部分反向有源掩模。 部分反向有源掩模将氧化物层的一部分暴露在大的有效区域上方和对准标记之上。 去除每个大活性区域的氧化物层和对准标记。 去除部分反向主动掩模。 氧化层平坦化。

公开(公告)号：US06743721B2

公开(公告)日：2004-06-01

申请号：US10166307

申请日：2002-06-10

申请人： Water Lur ,  David Lee ,  Kuang-Chih Wang

发明人： Water Lur ,  David Lee ,  Kuang-Chih Wang

IPC分类号： H01L2144

CPC分类号： H01L21/67167 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/67184 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  Y10T29/41

摘要： A cluster tool and a number of different processes for making a cobalt-silicide material are disclosed. Combinations of alloyed layers of Co—Ti— along with layers of Co— are arranged and heat treated so as to effectuate a silicide reaction. The resulting structures have extremely low resistance, and show little line width dependence, thus making them particularly attractive for use in semiconductor processing. A cluster tool is configured with appropriate sputter targets/heat assemblies to implement many of the needed operations for the silicide reactions, thus resulting in higher savings, productivity, etc.

摘要翻译： 公开了一种用于制造硅化钴材料的簇工具和许多不同的工艺。 Co-Ti合金层与Co层的组合进行排列并进行热处理，以实现硅化物反应。 所得到的结构具有极低的电阻，并且显示出很小的线宽依赖性，因此使它们对于用于半导体处理特别有吸引力。 集群工具配置有适当的溅射靶/热组件以实现硅化物反应的许多所需操作，从而导致更高的节省量，生产率等。

公开(公告)号：US6159845A

公开(公告)日：2000-12-12

申请号：US395906

申请日：1999-09-11

申请人： Tri-Rung Yew ,  Water Lur ,  Hsien-Ta Chung

发明人： Tri-Rung Yew ,  Water Lur ,  Hsien-Ta Chung

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76834 ,  H01L21/7681 ,  H01L21/7682 ,  H01L21/7684 ,  H01L21/76885

摘要： A dielectric layer in a dual-damascene interconnect is described. A dual-damascene interconnect structure is formed on a substrate. The dual-damascene interconnect structure has a first dielectric layer formed over the substrate, a second dielectric layer formed on the first dielectric layer, a first wire penetrating through the second dielectric layer and a second wire. The second wire penetrates through the second dielectric layer and is electrically coupled to the substrate. The second dielectric layer is removed. A barrier cap layer is formed conformally over the substrate. A third dielectric layer is formed on the barrier cap layer and an air gap is formed in a space enclosed by the third dielectric layer, the first and the second wires. A fourth dielectric layer is formed on the third dielectric layer. A planarizing process is performed to planarize the fourth dielectric layer.

摘要翻译： 描述双镶嵌互连中的电介质层。 在基板上形成双镶嵌互连结构。 所述双镶嵌互连结构具有形成在所述基板上的第一电介质层，形成在所述第一电介质层上的第二电介质层，穿过所述第二电介质层的第一电线和第二导线。 第二线穿透第二电介质层并且电耦合到衬底。 去除第二介电层。 保护层形成在衬底上。 第三电介质层形成在阻挡盖层上，并且在由第三电介质层，第一和第二电线围绕的空间中形成气隙。 在第三电介质层上形成第四电介质层。 执行平面化处理以平坦化第四介电层。