公开(公告)号：US20110090196A1

公开(公告)日：2011-04-21

申请号：US12754607

申请日：2010-04-06

Applicant: Yu-Hsuan Li ,  Yu-Jung Liu ,  Chun-Hung Kuo ,  Chun-Huai Li

Inventor： Yu-Hsuan Li ,  Yu-Jung Liu ,  Chun-Hung Kuo ,  Chun-Huai Li

IPC: G09G3/36

CPC classification number: G09G3/3648 ,  G09G2300/0857

Abstract: A liquid crystal display having pixel data self-retaining functionality includes a gate line for delivering a gate signal, a data line for delivering a data signal, a control unit for providing a first control signal and a second control signal, a data switch, a voltage-control inverter, a liquid crystal capacitor, and a pass transistor. The data switch is utilized for inputting the data signal to become a first data signal according to the gate signal. The voltage-control inverter is utilized for inverting the first data signal to generate a second data signal furnished to the liquid crystal capacitor according to the enable operation of the first control signal. The pass transistor is used for passing the second data signal to become the first data signal or for passing the first data signal to become the second data signal according to the second control signal.

Abstract translation: 具有像素数据自保持功能的液晶显示器包括用于传送栅极信号的栅极线，用于传送数据信号的数据线，用于提供第一控制信号和第二控制信号的控制单元，数据开关， 电压控制逆变器，液晶电容器和通过晶体管。 数据开关用于根据门信号输入数据信号成为第一数据信号。 电压控制逆变器用于使第一数据信号反相，以根据第一控制信号的使能操作产生提供给液晶电容器的第二数据信号。 通过晶体管用于使第二数据信号通过以成为第一数据信号，或者根据第二控制信号使第一数据信号变为第二数据信号。

公开(公告)号：US07928938B2

公开(公告)日：2011-04-19

申请号：US11278790

申请日：2006-04-05

Applicant: Mitsuaki Osame ,  Aya Anzai

Inventor： Mitsuaki Osame ,  Aya Anzai

IPC: G09G3/32

CPC classification number: G09G3/3258 ,  G09G3/2022 ,  G09G2300/0857 ,  G09G2310/0251 ,  G09G2320/0223 ,  G09G2330/023

Abstract: A semiconductor device of the invention includes a data line, a power source line, a first scan line, a second scan line, a first transistor, a second transistor, a memory circuit, a third transistor, and a light-emitting element. A gate of the first transistor is connected to the data line, and a first terminal thereof is connected to the power source line; a gate of the second transistor is connected to the first scan line, and a first terminal thereof is connected to a second terminal of the first transistor; the memory circuit is connected to a second terminal of the second transistor and the second scan line; a first terminal of the third transistor is connected to the light-emitting element; and the memory circuit holds a first potential inputted from the power source line or a second potential inputted from the second scan line, and applies the potential to a gate of the third transistor to control emission/non-emission of the light-emitting element.

Abstract translation: 本发明的半导体器件包括数据线，电源线，第一扫描线，第二扫描线，第一晶体管，第二晶体管，存储电路，第三晶体管和发光元件。 第一晶体管的栅极连接到数据线，其第一端连接到电源线; 第二晶体管的栅极连接到第一扫描线，其第一端连接到第一晶体管的第二端; 存储电路连接到第二晶体管和第二扫描线的第二端子; 第三晶体管的第一端子连接到发光元件; 并且存储电路保持从电源线输入的第一电位或从第二扫描线输入的第二电位，并且将电位施加到第三晶体管的栅极以控制发光元件的发射/不发光。

公开(公告)号：US07924274B2

公开(公告)日：2011-04-12

申请号：US11383056

申请日：2006-05-12

Applicant: Karl M. Guttag

Inventor： Karl M. Guttag

IPC: G09G5/00

CPC classification number: G09G5/10 ,  G06F3/147 ,  G09G3/2014 ,  G09G3/2022 ,  G09G3/34 ,  G09G3/346 ,  G09G2300/0809 ,  G09G2300/0857 ,  G09G2310/0221 ,  G09G2310/0275

Abstract: The present invention provides a various methods, systems and devices for controlling light modulating elements and/or spatial light modulators. In some embodiments of the present invention, a recursive feedback method is used to control light modulating elements and/or spatial light modulators.

Abstract translation: 本发明提供了用于控制光调制元件和/或空间光调制器的各种方法，系统和装置。 在本发明的一些实施例中，使用递归反馈方法来控制光调制元件和/或空间光调制器。

公开(公告)号：US07903104B2

公开(公告)日：2011-03-08

申请号：US11689464

申请日：2007-03-21

Applicant: Chih-Liang Chen ,  Alex Hung-Pin Sun

Inventor： Chih-Liang Chen ,  Alex Hung-Pin Sun

IPC: G09G3/34

CPC classification number: G09G3/346 ,  G09G3/2033 ,  G09G2300/0857 ,  G09G2310/0289 ,  G09G2320/0252

Abstract: A spatial light modulator having two static random access memory (SRAM) devices, including a display controller configured with a display sequence, the display sequence including a first display slice and a second display slice, the first display slice having a display time less than two times a minimum time period determined by the time of a write event, and the second display slice having a display time of more than two times the minimum time period. The controller controls write events from the two SRAM devices, and the first display slice and second display slice are ordered in the display sequence so that the controller causes the spatial light modulator to output light and causes the two SRAM devices each to perform a write event during the second display slice.

Abstract translation: 一种具有两个静态随机存取存储器（SRAM）装置的空间光调制器，包括配置有显示序列的显示控制器，所述显示序列包括第一显示切片和第二显示切片，所述第一显示切片具有小于二的显示时间 乘以由写入事件的时间确定的最小时间段，并且第二显示切片具有超过最小时间段的两倍的显示时间。 控制器控制来自两个SRAM器件的写入事件，并且第一显示切片和第二显示切片以显示顺序排列，使得控制器使空间光调制器输出光，并使两个SRAM器件各自执行写入事件 在第二显示切片期间。

公开(公告)号：US07847756B2

公开(公告)日：2010-12-07

申请号：US10884958

申请日：2004-07-07

Applicant: Yoshihito Ishibashi ,  Masayuki Takada ,  Shinya Saito

Inventor： Yoshihito Ishibashi ,  Masayuki Takada ,  Shinya Saito

IPC: G09G3/00

CPC classification number: G09G3/003 ,  G09G3/005 ,  G09G3/3258 ,  G09G3/3266 ,  G09G3/3275 ,  G09G5/006 ,  G09G2300/0857 ,  G09G2340/02 ,  H01L27/3244 ,  H01L2251/5315 ,  H01L2251/5323 ,  H04N13/243 ,  H04N13/275 ,  H04N13/393 ,  H04N13/398

Abstract: A three-dimensional image display apparatus which displays a three-dimensional image as a set of two-dimensional images by switching and displaying the two-dimensional images on a rotating self-luminous two-dimensional display panel while synchronizing with the rotation angle of the two-dimensional display panel. This three-dimensional image display apparatus comprises a rotation body for rotating the two-dimensional display panel while fixing and supporting, a support body for rotatably supporting the rotation body, compressing image data on the support body to display the two-dimensional image on the two-dimensional display panel, transmitting the compressed image data from the support body to the rotation body side, receiving the transmitted compression image data on the rotation body, and expanding the received compression image data on the rotation body so as to restore an original image data. The support body is external to the rotation body, and includes drive coils which generate a repulsive and an attractive force with magnets in the rotation body.

Abstract translation: 一种三维图像显示装置，其通过在旋转的自发光二维显示面板上切换和显示二维图像同时与三维图像的旋转角度同步地将三维图像显示为一组二维图像 二维显示面板。 该三维图像显示装置包括用于在固定和支撑的同时旋转二维显示面板的旋转体，用于可旋转地支撑旋转体的支撑体，压缩支撑体上的图像数据以将二维图像显示在 将压缩图像数据从支撑体传送到旋转体侧，在旋转体上接收发送的压缩图像数据，并将接收到的压缩图像数据扩展到旋转体上，以恢复原始图像 数据。 支撑体在旋转体的外部，并且包括在旋转体中产生具有排斥力和吸引力的磁体的驱动线圈。

公开(公告)号：US07833851B2

公开(公告)日：2010-11-16

申请号：US11987311

申请日：2007-11-29

Applicant: Hideaki Kuwabara ,  Koichiro Tanaka

Inventor： Hideaki Kuwabara ,  Koichiro Tanaka

IPC: H01L21/84

CPC classification number: H01L27/1251 ,  G09G3/3208 ,  G09G2300/0857 ,  H01L27/1214 ,  H01L27/1233 ,  H01L27/127 ,  H01L27/3244 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/78621 ,  H01L29/78648

Abstract: It is an object of the invention that, in semiconductor device, in order to promote the tendency of miniaturization of each display pixel pitch, which will be resulted in with the tendency toward the higher precision (increase of pixel number) and further miniaturizations, a plurality of elements is formed within a limited area and the area occupied by the elements is compacted so as to be integrated. A plurality of semiconductor layers 13, 15 is formed on different layers with insulating film 14 sandwiched therebetween. After carrying out crystallization by means of laser beam, on each semiconductor layer (semiconductor layers 16, 17 having crystal structure respectively), an N-channel type TFT of inversed stagger structure and a P-channel type TFT 30 of top gate structure are formed respectively and integrated so that the size of CMOS circuit is miniaturized.

Abstract translation: 本发明的目的在于，在半导体装置中，为了提高每个显示像素间距的小型化的趋势，这将随着更高的精度（像素数的增加）和进一步的小型化的趋势而导致， 在有限的区域内形成多个元件，并且元件所占据的区域被压实成一体。 多个半导体层13,15形成在夹着绝缘膜14的不同层上。 在通过激光束进行结晶之后，在每个半导体层（分别具有晶体结构的半导体层16,17）上形成反向交错结构的N沟道型TFT和顶栅结构的P沟道型TFT 30 并且集成使得CMOS电路的尺寸小型化。

公开(公告)号：US20100245212A1

公开(公告)日：2010-09-30

申请号：US12815108

申请日：2010-06-14

Applicant: JAMES M. DALLAS ,  DAVID B. HOLLENBECK ,  PER HAROLD LARSEN ,  RAINER M. MALZBENDER ,  Earle R. Vickery, III ,  Michael Wayne Yee

Inventor： JAMES M. DALLAS ,  DAVID B. HOLLENBECK ,  PER HAROLD LARSEN ,  RAINER M. MALZBENDER ,  Earle R. Vickery, III ,  Michael Wayne Yee

IPC: G09G3/00

CPC classification number: G09G5/00 ,  G02F1/133553 ,  G09G3/20 ,  G09G3/2003 ,  G09G3/2014 ,  G09G3/2059 ,  G09G3/2088 ,  G09G3/3413 ,  G09G3/3651 ,  G09G3/3685 ,  G09G3/3688 ,  G09G5/02 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2300/0809 ,  G09G2300/0857 ,  G09G2310/0221 ,  G09G2310/0235 ,  G09G2310/0259 ,  G09G2310/027 ,  G09G2310/0275 ,  G09G2310/0289 ,  G09G2310/061 ,  G09G2320/041 ,  G09G2320/0666 ,  G09G2330/021 ,  G09G2340/02 ,  G09G2340/0407 ,  G11C11/417

Abstract: A microdisplay having interface circuitry on the same silicon backplane to allow it to receive digital images and video in a variety of formats and convert same to field sequential color signals for generation of full color images. It includes column data processors having a comparator for each block of N-columns of pixels. Image data is double-buffered in SRAM memory cells located beneath the pixel electrodes, but not within each pixel. The stored data is logically associated with each pixel via the column data processors. Image compression is accomplished by converting RGB data to a variant of YUV data and sampling the color components of the converted data less frequently than the luminance components. The SRAM image buffer consumes a reduced amount of power. A temperature compensation scheme allows the temperature of the microdisplay to be sensed and the drive voltage to the pixel electrodes to be varied in response thereto.

Abstract translation: 具有在相同硅背板上的接口电路的微型显示器，以允许其以各种格式接收数字图像和视频，并将其转换为场顺序彩色信号以产生全色图像。 它包括具有用于N列像素的每个块的比较器的列数据处理器。 图像数据在位于像素电极下方的SRAM存储器单元中双缓冲，但不在每个像素内。 存储的数据通过列数据处理器与每个像素逻辑关联。 图像压缩通过将RGB数据转换为YUV数据的变体并且比亮度分量更频繁地对转换的数据的颜色分量进行采样来实现。 SRAM图像缓冲器消耗了较少的功率。 温度补偿方案允许感测微显示器的温度，并且响应于像素电极的驱动电压变化。

公开(公告)号：US07692671B2

公开(公告)日：2010-04-06

申请号：US11172382

申请日：2005-06-30

Applicant: Sunny Yat-san Ng

Inventor： Sunny Yat-san Ng

IPC: G09G5/10

CPC classification number: G09G3/3677 ,  G09G3/2014 ,  G09G3/2022 ,  G09G3/2029 ,  G09G3/2033 ,  G09G3/2037 ,  G09G3/2092 ,  G09G3/3611 ,  G09G3/3614 ,  G09G3/3648 ,  G09G3/3685 ,  G09G3/3688 ,  G09G5/399 ,  G09G2300/0809 ,  G09G2300/0857 ,  G09G2310/0205 ,  G09G2310/0218 ,  G09G2310/0227 ,  G09G2310/0275 ,  G09G2310/08 ,  G09G2320/02 ,  G09G2330/026 ,  G09G2360/18

Abstract: A novel method for asynchronously driving a display device including a plurality of pixels arranged in a plurality of columns and a plurality of rows includes the steps of receiving a first multi-bit data word indicative of a first grayscale value to be displayed on a pixel of a first row of the display, defining a first time period during which an electrical signal corresponding to the first grayscale value can be asserted on the pixel of said first row, receiving a second multi-bit data word indicative of a second grayscale value to be displayed on a pixel of a second row of the display, and defining a second time period that is temporally offset from the first time period during which an electrical signal corresponding to the second grayscale value can be asserted on the pixel of said second row. A novel display driver for performing the methods of the present invention is also disclosed.

Abstract translation: 一种用于异步驱动包括布置在多列和多行中的多个像素的显示装置的新颖方法包括以下步骤：接收指示将要显示在像素上的第一灰度值的第一多位数据字 定义第一时间段，在该第一时间段期间，可以在所述第一行的像素上断言对应于第一灰阶值的电信号，接收指示第二灰度值的第二多位数据字为 显示在显示器的第二行的像素上，并且定义从第一时间段暂时偏移的第二时间段，在该第一时间段期间，可以在所述第二行的像素上断言对应于第二灰阶值的电信号。 还公开了用于执行本发明的方法的新型显示驱动器。

公开(公告)号：US20100079422A1

公开(公告)日：2010-04-01

申请号：US12552414

申请日：2009-09-02

Applicant: Yasuhiro Shimodaira

Inventor： Yasuhiro Shimodaira

IPC: G09G5/00 ,  G09G3/34

CPC classification number: G09G3/344 ,  G09G2300/0857 ,  G09G2310/027 ,  G09G2310/0294 ,  G09G2330/025

Abstract: A driving circuit is provided which is applied to a matrix device having a plurality of functional elements arranged in a matrix, which is connected to the functional elements via data lines, and which has a plurality of blocks. The driving circuit includes a shift register which has a plurality of register sections, each of the register sections being corresponding to one of the plurality of blocks; a data signal line; a first data latch circuit connected to an output terminal of the shift register and the data signal line; and a second data latch circuit connected to the output terminal of the shift register and an output terminal of the first data latch circuit, and connected to the data line directly or via another circuit. The first and second data latch circuits are respectively divided into multistage operation units. Each of the operation units is corresponding to the one data line or the plurality of data lines and is corresponding to one of the plurality of blocks. An output terminal of the shift register belonging to a block B is connected to the operation unit of the first data latch circuit belonging to the block B, the output terminal of the shift register belonging to a block A is connected to the operation unit of the second data latch circuit belonging to the block B, and each of the block A and block B is one of the plurality of blocks.

Abstract translation: 提供一种驱动电路，其被施加到具有以矩阵形式布置的多个功能元件的矩阵装置，矩阵装置通过数据线连接到功能元件，并具有多个块。 驱动电路包括具有多个寄存器部分的移位寄存器，每个寄存器部分对应于多个块中的一个; 数据信号线 连接到移位寄存器的输出端和数据信号线的第一数据锁存电路; 以及第二数据锁存电路，连接到移位寄存器的输出端和第一数据锁存电路的输出端，并且直接或经由另一电路连接到数据线。 第一和第二数据锁存电路分别分成多级操作单元。 每个操作单元对应于一个数据线或多个数据线，并且对应于多个块中的一个。 属于块B的移位寄存器的输出端子连接到属于块B的第一数据锁存电路的操作单元，属于块A的移位寄存器的输出端连接到 属于块B的第二数据锁存电路，块A和块B中的每一个是多个块中的一个。

公开(公告)号：US20090303173A1

公开(公告)日：2009-12-10

申请号：US12430493

申请日：2009-04-27

Applicant: Kiichi KAJINO

Inventor： Kiichi KAJINO

IPC: G09G3/34 ,  G09G5/00

CPC classification number: G09G3/344 ,  G09G2300/0857 ,  G09G2310/04 ,  G09G2330/021 ,  G09G2330/028

Abstract: An electrophoretic display apparatus includes a display having a plurality of pixels each having a pixel electrode; and a common electrode opposed to the pixel electrode; an electrophoretic element disposed between the pixel electrode and the common electrode, the electrophoretic element containing electrophoretic particles; a driving unit that performs partial rewrite driving to partially rewrite an image displayed on the display by applying a drive voltage between the pixel electrode and the common electrode in part of the plurality of pixels on the basis of image data; a power supply circuit that increases power supply voltage and supplies the drive voltage to the driving unit; and a control unit that controls the power supply circuit so as to change the drive-voltage supply capacity of the power supply circuit in accordance with the area of a rewritten region that the part of the pixels occupies in the display.

Abstract translation: 电泳显示装置包括具有多个像素的显示器，每个像素具有像素电极; 和与像素电极相对的公共电极; 设置在所述像素电极和所述公共电极之间的电泳元件，所述电泳元件包含电泳粒子; 驱动单元，其通过基于图像数据在所述多个像素的一部分中施加所述像素电极和所述公共电极之间的驱动电压来进行部分重写驱动以部分地重写显示在所述显示器上的图像; 电源电路，其增加电源电压并将驱动电压提供给所述驱动单元; 以及控制单元，其控制所述电源电路，以便根据所述一部分像素在显示器中占据的重写区域的面积来改变所述电源电路的驱动电压供应容量。