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    NOR-BASED GRAYSCALE FOR A DIGITAL DISPLAY
    1.
    发明申请
    NOR-BASED GRAYSCALE FOR A DIGITAL DISPLAY 审中-公开
    用于数字显示的基于NOR的灰度图

    公开(公告)号：US20120069060A1

    公开(公告)日：2012-03-22

    申请号：US13247021

    申请日：2011-09-28

    申请人： Mark A. Handschy ,  James M. Dallas ,  Per Harold Larsen ,  David B. Hollenbeck

    发明人： Mark A. Handschy ,  James M. Dallas ,  Per Harold Larsen ,  David B. Hollenbeck

    IPC分类号： G09G3/36 ,  G09G5/10

    CPC分类号： G09G3/3629 ,  G09G3/2014 ,  G09G3/3618 ,  G09G2300/0809 ,  G09G2300/0857 ,  G09G2310/0235 ,  G09G2320/0285 ,  G09G2320/0673

    摘要： A digital display provides pulse-width-modulated pixel waveforms by applying a wired-NOR function to selected bits of stored image data. Image bits are selected according to a digital sequence and the wired-NOR function results in a trigger signal that may be used to switch the state of a pixel element. The pixel element may be a pixel state latch of a pixel driver circuit. The digital display may accept conventional 24-bit color video signals (one 8-bit gray-scale value for each pixel for each of the red, green, and blue primary colors), and convert this input signal to sequential color with PWM digital gray scale drive to each pixel.

    摘要翻译： 数字显示器通过对所存储的图像数据的选定位应用有线NOR功能来提供脉冲宽度调制的像素波形。 根据数字序列选择图像位，并且有线NOR功能产生可用于切换像素元件的状态的触发信号。 像素元件可以是像素驱动器电路的像素状态锁存器。 数字显示器可以接受常规的24位彩色视频信号（每个红色，绿色和蓝色原色的每个像素的一个8位灰度值），并将该输入信号转换成具有PWM数字灰度的顺序颜色 对每个像素进行刻度驱动。

    Termination structure based on the cancellation of the reflected wave
    3.
    发明授权
    Termination structure based on the cancellation of the reflected wave 失效
    基于消除反射波的终止结构

    公开(公告)号：US06246721B1

    公开(公告)日：2001-06-12

    申请号：US08935012

    申请日：1997-09-22

    申请人： Johnny Q. Zhang ,  David B. Hollenbeck

    发明人： Johnny Q. Zhang ,  David B. Hollenbeck

    IPC分类号： H04B300

    CPC分类号： G06F13/4086 ,  G06F1/10 ,  H04L25/0298

    摘要： A termination structure is shown whereby multiple transmission lines designed to have the same intrinsic impedance and same delay are driven from a central node. The central node is driven by a driver and calibration resistor connected in series to produce a drive impedance that is equal to the parallel combination of the intrinsic impedances of the multiple transmission lines. At the other end of the multiple transmission lines is a receiver and a feedback circuit. The feedback circuit provides a modest amount of positive feedback from the output of the receiver to the input of the receiver. This positive feedback prevents the output of the receiver from being affected by small reflections and perturbations that result from mismatches among the multiple transmission lines.

    摘要翻译： 示出了终端结构，其中设计成具有相同的固有阻抗和相同延迟的多条传输线路从中心节点驱动。 中心节点由串联连接的驱动器和校准电阻驱动，以产生等于多条传输线的本征阻抗的并联组合的驱动阻抗。 在多条传输线的另一端是接收机和反馈电路。 反馈电路提供从接收器的输出到接收器的输入的适量的正反馈。 这种正反馈防止接收机的输出受到由多个传输线之间的不匹配引起的小的反射和扰动的影响。

    Package routing of integrated circuit signals
    4.
    发明授权
    Package routing of integrated circuit signals 有权
    集成电路信号的封装路由

    公开(公告)号：US6161215A

    公开(公告)日：2000-12-12

    申请号：US144299

    申请日：1998-08-31

    申请人： David B. Hollenbeck ,  William S. Worley, Jr. ,  David W. Quint ,  Timothy L. Michalka

    发明人： David B. Hollenbeck ,  William S. Worley, Jr. ,  David W. Quint ,  Timothy L. Michalka

    IPC分类号： H01L21/822 ,  G06F1/10 ,  G06F17/50 ,  H01L23/498 ,  H01L23/64 ,  H01L27/04

    CPC分类号： G06F1/10 ,  G06F17/5077 ,  H01L23/49838 ,  H01L23/64 ,  H01L2224/17181 ,  H01L2924/00014 ,  H01L2924/15173 ,  H01L2924/3011 ,  H01L2224/0401

    摘要： Signal delay and skew within an integrated circuit are minimized when 1) signals are distributed to distant points of an integrated circuit via a layer of its package, and 2) traces in the package layer are etched and treated as transmission lines. As disclosed herein, a signal is driven through a first connection between an integrated circuit and an integrated circuit package layer. The signal is then distributed to one or more additional connections between the integrated circuit and the integrated circuit package layer, by means of point-to-point transmission lines formed in the integrated circuit package layer, each of the transmission lines being terminated at one or both ends by impedances which are substantially matched to the characteristic impedance of the transmission line to which they are attached. The signal is then received into the integrated circuit through the one or more additional connections between the integrated circuit and the integrated circuit package layer.

    摘要翻译： 当1）信号通过其封装层分布到集成电路的远端时，集成电路内的信号延迟和偏移被最小化，2）封装层中的迹线被蚀刻并被处理为传输线。 如本文所公开的，信号通过集成电路和集成电路封装层之间的第一连接被驱动。 然后，通过形成在集成电路封装层中的点对点传输线，将信号分配到集成电路和集成电路封装层之间的一个或多个附加连接，每条传输线以一个或多个 两端的阻抗基本上与其所连接的传输线的特性阻抗相匹配。 然后，该信号通过集成电路和集成电路封装层之间的一个或多个附加连接被接收到集成电路中。

    Clock buffer circuit having short propagation delay
    7.
    发明授权
    Clock buffer circuit having short propagation delay 失效
    时钟缓冲电路具有较短的传播延迟

    公开(公告)号：US06538488B2

    公开(公告)日：2003-03-25

    申请号：US09426874

    申请日：1999-10-26

    申请人： Johnny Q Zhang ,  David B Hollenbeck

    发明人： Johnny Q Zhang ,  David B Hollenbeck

    IPC分类号： G06F104

    CPC分类号： H03K19/018521 ,  G06F1/10

    摘要： A clock buffer circuit having a reduced propagation delay therethrough. The clock buffer circuit has a clock input for receiving an initial clock pulse thereto, and a clock output for transmitting a buffered clock pulse therethrough. A first driver chain arrangement of transistors is coupled with the clock input and the clock output for switching the buffered clock pulse from a low voltage level to a high voltage level. A second driver chain arrangement of transistors is coupled with the clock input and the clock output for switching the buffered clock pulse from the high voltage level to the low voltage level. A holder circuit and a first and trigger circuit for the second driver chain are also included.

    摘要翻译： 具有减小的传播延迟的时钟缓冲电路。 时钟缓冲电路具有用于接收初始时钟脉冲的时钟输入和用于发送经缓冲的时钟脉冲的时钟输出。 晶体管的第一驱动器链配置与时钟输入和时钟输出耦合，用于将缓冲的时钟脉冲从低电压电平切换到高电压电平。 晶体管的第二驱动器链配置与时钟输入和时钟输出耦合，用于将缓冲的时钟脉冲从高电压电平切换到低电压电平。 还包括用于第二驱动器链的保持器电路和第一触发器电路。

    Delay elements arranged for a signal controlled oscillator
    8.
    发明授权
    Delay elements arranged for a signal controlled oscillator 失效
    布置为信号控制振荡器的延迟元件

    公开(公告)号：US6157266A

    公开(公告)日：2000-12-05

    申请号：US22464

    申请日：1998-02-12

    申请人： Li Ching Tsai ,  Johnny Q. Zhang ,  David B. Hollenbeck

    发明人： Li Ching Tsai ,  Johnny Q. Zhang ,  David B. Hollenbeck

    IPC分类号： H03K3/354 ,  H03B5/08 ,  H03K3/0231 ,  H03B5/24

    CPC分类号： H03K3/0231

    摘要： A ring-type signal controlled oscillator comprising a series of active delay elements, each including a respective differential pair of transistors. The inputs and outputs of the differential pair transistors are interconnected in a closed ring to produce oscillations at a frequency determined by the delay of each delay element. The differential pair of transistors further has a pair of current source inputs for controlling an amount of delay of the delay element, and a pair of load inputs for stabilizing the amount of delay. The invention advantageously provides high frequency operation with substantially symmetric rise and fall time, while limiting spread in oscillation frequency and spread in amplitude in relation to fabrication process variability and power supply variability.

    摘要翻译： 一种环形信号控制振荡器，包括一系列有源延迟元件，每个有源延迟元件均包括相应的差分对晶体管。 差分对晶体管的输入和输出在闭环中互连以产生由每个延迟元件的延迟确定的频率的振荡。 晶体管的差分对还具有用于控制延迟元件的延迟量的一对电流源输入端和用于稳定延迟量的一对负载输入。 本发明有利地提供具有基本对称的上升和下降时间的高频操作，同时限制振荡频率的扩展并且相对于制造工艺变化性和电源变化性而在幅度上扩展。