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246 条记录 (耗时 0.041 秒)

    Ferroelectric memory having ferroelectric capacitor insulative film
    72.
    发明授权
    Ferroelectric memory having ferroelectric capacitor insulative film 有权
    具有铁电电容器绝缘膜的铁电存储器

    公开(公告)号：US06958508B2

    公开(公告)日：2005-10-25

    申请号：US09968948

    申请日：2001-10-03

    申请人： Takumi Mikawa

    发明人： Takumi Mikawa

    IPC分类号： H01L21/02 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8239 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115 ,  H01L27/108

    CPC分类号： H01L27/11509 ,  H01L21/28568 ,  H01L21/76895 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/60 ,  H01L28/75

    摘要： A capacitor upper electrode and a wiring are electrically connected to each other by using a plug and a conductive layer formed below a capacitive element without using a plug that directly connects the capacitor upper electrode to the wiring provided thereon via an interlayer insulating film therebetween. Alternatively, the capacitor upper electrode is covered by a conductive hydrogen barrier film, and the capacitor upper electrode and the wiring are electrically connected to each other via both a plug connecting the wiring and the conductive hydrogen barrier film to each other and the conductive hydrogen barrier film.

    摘要翻译： 电容器上电极和布线通过使用形成在电容元件下方的插塞和导电层而彼此电连接，而不使用通过其间的层间绝缘膜将电容器上电极直接连接到设置在其上的布线的插头。 或者，电容器上电极被导电氢阻挡膜覆盖，并且电容器上电极和布线通过将布线和导电氢阻挡膜彼此连接的插塞彼此电连接，并且导电氢屏障 电影。

    Semiconductor memory device and method of manufacturing the same
    73.
    发明申请
    Semiconductor memory device and method of manufacturing the same 失效
    半导体存储器件及其制造方法

    公开(公告)号：US20050118795A1

    公开(公告)日：2005-06-02

    申请号：US10885749

    申请日：2004-07-08

    申请人： Osamu Hidaka ,  Iwao Kunishima ,  Hiroyuki Kanaya

    发明人： Osamu Hidaka ,  Iwao Kunishima ,  Hiroyuki Kanaya

    IPC分类号： H01L27/10 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8246 ,  H01L27/105

    CPC分类号： H01L27/11502 ,  H01L21/76802 ,  H01L27/105 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/55

    摘要： A semiconductor memory device includes a semiconductor substrate having a first region and a second region, a transistor placed in the first region of the semiconductor substrate, a first insulating film formed on the semiconductor substrate in the first and second regions and on the transistor, a first ferroelectric capacitor formed on the first insulating film in the first region and electrically connected to the transistor, a hydrogen barrier film formed above the first ferroelectric capacitor and above the first insulating film in the first and second regions, a first contact penetrating the hydrogen barrier film in the first region and electrically connected to the first ferroelectric capacitor, and a second contact which penetrates the hydrogen barrier film in the second region and which is in a floating state.

    摘要翻译： 半导体存储器件包括具有第一区域和第二区域的半导体衬底，放置在半导体衬底的第一区域中的晶体管，在第一和第二区域中的晶体管上形成在半导体衬底上的第一绝缘膜， 形成在第一区域的第一绝缘膜上并与晶体管电连接的第一铁电电容器，形成在第一铁电电容器上方的第一和第二区域上的第一绝缘膜上方的氢阻挡膜， 并且电连接到第一铁电电容器，以及第二触点，其穿过第二区域中的氢阻挡膜并处于浮置状态。

    Ferroelectronic memory and electronic apparatus
    75.
    发明授权
    Ferroelectronic memory and electronic apparatus 失效
    铁电记忆体和电子仪器

    公开(公告)号：US06737690B2

    公开(公告)日：2004-05-18

    申请号：US10105042

    申请日：2002-03-22

    申请人： Takamitsu Higuchi ,  Setsuya Iwashita ,  Hiromu Miyazawa ,  Kazumasa Hasegawa ,  Eiji Natori

    发明人： Takamitsu Higuchi ,  Setsuya Iwashita ,  Hiromu Miyazawa ,  Kazumasa Hasegawa ,  Eiji Natori

    IPC分类号： H01C31119

    CPC分类号： H01L27/11502 ,  H01L21/02197 ,  H01L21/31604 ,  H01L27/105 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/55 ,  H01L28/60 ,  Y10S257/906

    摘要： The present invention relates to a ferroelectric memory having a matrix-type memory cell array which has an excellent degree of integration, in which the angularity of the ferroelectric layer's hysteresis curve is improved. A ferroelectric memory having both integration and memory characteristics in which the angularity of the ferroelectric layer's hysteresis curve is improved is realized as follows. Namely, a structure is employed in which the memory cell array and the peripheral circuit are in a plane separated from one another, and the ferroelectric layer is made to undergo epitaxial growth on to a Si single crystal via a buffer and the first signal electrodes.

    摘要翻译： 本发明涉及具有优异的集成度的矩阵型存储单元阵列的铁电存储器，其中提高了铁电层磁滞曲线的角度。 如下实现具有集成和存储特性的强电介质存储器，其中铁电层的磁滞曲线的角度得到改善。 也就是说，采用其中存储单元阵列和外围电路处于彼此分离的平面中的结构，并且使铁电层经由缓冲器和第一信号电极经历外延生长到Si单晶。

    Semiconductor device and method of manufcaturing the same
    78.
    发明申请
    Semiconductor device and method of manufcaturing the same 失效
    半导体器件及其制作方法

    公开(公告)号：US20020130345A1

    公开(公告)日：2002-09-19

    申请号：US09971737

    申请日：2001-10-09

    申请人： Fujitsu Limited

    发明人： Kaoru Saigoh ,  Hisashi Miyazawa ,  Hirokazu Yamazaki ,  Hideaki Suzuki

    IPC分类号： H01L029/94

    CPC分类号： H01L27/11502 ,  H01L27/0629 ,  H01L27/105 ,  H01L27/11507 ,  H01L27/11509

    摘要： The semiconductor device having the capacitor comprises a plurality of switching elements formed on a semiconductor substrate 1 at a distance, a plurality of capacitors formed in areas between a plurality of switching elements formed in the first direction respectively and each having a lower electrode, a dielectric film and an upper electrode, first wirings for connecting the upper electrodes of the capacitors and the switching elements in the first direction on a one-by-one base, and second wirings formed over a part of the first wirings, the switching elements, and the capacitors to extend in the second direction that intersects with the first direction. Accordingly, the higher speed operation than the prior art can be achieved.

    摘要翻译： 具有电容器的半导体器件包括在半导体衬底1上形成一定距离的多个开关元件，多个电容器形成在分别形成在第一方向上的多个开关元件之间的区域中，并且各自具有下电极，电介质 薄膜和上电极，第一布线，用于在一个接一个的基底上连接电容器的上电极和第一方向的开关元件，以及形成在第一布线的一部分上的第二布线，开关元件和 电容器沿与第一方向相交的第二方向延伸。 因此，可以实现比现有技术更高的速度操作。

    Method for manufacturing a ferroelectric memory device
    80.
    发明授权
    Method for manufacturing a ferroelectric memory device 有权
    铁电存储器件的制造方法

    公开(公告)号：US06410345B1

    公开(公告)日：2002-06-25

    申请号：US09975086

    申请日：2001-10-12

    申请人： Won Moon ,  Jeong-Ho Cho

    发明人： Won Moon ,  Jeong-Ho Cho

    IPC分类号： H01L2100

    CPC分类号： H01L27/11502 ,  H01L27/105 ,  H01L27/11507 ,  H01L27/11509

    摘要： A ferroelectric memory device manufacturing method capable of improving topology between a ferroelectric memory device and a logic device. The method for manufacturing the ferroelectric memory device includes steps of: a) forming an insulating layer on a semiconductor substrate; b) opening a capacitor region by selectively patterning the insulating layer; c) forming a bottom electrode in the opened capacitor region by using a chemical vapor deposition (CVD) method; d) forming a ferroelectric layer on a subsequent insulating layer including the bottom electrode; e) filling the ferroelectric layer on the capacitor region to a same height as that of the subsequent insulating layer surface; and f) forming a top electrode on the ferroelectric layer.

    摘要翻译： 一种能够改善铁电存储器件和逻辑器件之间的拓扑结构的铁电存储器件制造方法。 制造铁电存储器件的方法包括以下步骤：a）在半导体衬底上形成绝缘层; b）通过选择性地图案化绝缘层来打开电容器区域; c）通过使用化学气相沉积（CVD）方法在开放的电容器区域中形成底部电极; d）在包括底部电极的后续绝缘层上形成铁电层; e）将电容器区域上的铁电层填充到与随后的绝缘层表面相同的高度; 以及f）在所述铁电层上形成顶部电极。