公开(公告)号：US20150171104A1

公开(公告)日：2015-06-18

申请号：US14305122

申请日：2014-06-16

申请人： Cypress Semiconductor Corporation

发明人： Venkatraman Prabhakar ,  Krishnaswamy Ramkumar ,  Igor Kouznetsov

IPC分类号： H01L27/115 ,  H01L21/266

CPC分类号： H01L27/11573 ,  H01L21/823462 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/40117 ,  H01L29/4234

摘要： Methods of integrating complementary SONOS devices into a CMOS process flow are described. In one embodiment, the method begins with depositing a hardmask (HM) over a substrate including a first-SONOS region and a second-SONOS region. A first tunnel mask (TUNM) is formed over the HM exposing a first portion of the HM in the second-SONOS region. The first portion of the HM is etched, a channel for a first SONOS device implanted through a first pad oxide overlying the second-SONOS region and the first TUNM removed. A second TUNM is formed exposing a second portion of the HM in the first-SONOS region. The second portion of the HM is etched, a channel for a second SONOS device implanted through a second pad oxide overlying the first-SONOS region and the second TUNM removed. The first and second pad oxides are concurrently etched, and the HM removed.

摘要翻译： 描述了将互补SONOS器件集成到CMOS工艺流程中的方法。 在一个实施例中，该方法开始于在包括第一SONOS区域和第二SONOS区域的衬底上沉积硬掩模（HM）。 在HM上形成第一隧道掩模（TUNM），暴露第二SONOS区域中的HM的第一部分。 蚀刻HM的第一部分，通过覆盖第二SONOS区域并且移除第一TUNM的第一衬垫氧化物注入第一SONOS器件的沟道。 第二TUNM被形成为暴露在第一SONOS区域中的HM的第二部分。 蚀刻HM的第二部分，通过覆盖第一SONOS区域并且移除第二TOSM的第二衬垫氧化物注入第二SONOS器件的沟道。 同时蚀刻第一和第二垫氧化物，并除去HM。

公开(公告)号：US20150060985A1

公开(公告)日：2015-03-05

申请号：US14202501

申请日：2014-03-10

申请人： Kabushiki Kaisha Toshiba

发明人： Takashi Kobayashi ,  Daina Inoue ,  Hideto Takekida

IPC分类号： H01L29/423 ,  H01L21/28

CPC分类号： H01L29/40117 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11573 ,  H01L28/20 ,  H01L29/40114

摘要： According to one embodiment, nonvolatile semiconductor memory device includes: a semiconductor layer; element regions separated the semiconductor layer, the element regions; and a memory cell including a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate electrode provided above the element regions, a peripheral region including a resistance element including a resistance element layer provided above the semiconductor layer via a first insulating film, a dummy layer provided on a part of the resistance element layer via a second insulating film, a third insulating film provided on the resistance element layer at a first distance from the dummy layer, a fourth insulating film provided on the semiconductor layer at a second distance from the resistance element layer, and a contact piercing the third insulating film, and connected to the resistance element layer, the first distance being shorter than the second distance.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括：半导体层; 元件区域分离半导体层，元件区域; 以及包括设置在元件区域上方的第一栅极绝缘膜，电荷存储层，第二栅极绝缘膜和控制栅电极的存储单元，包括设置在半导体层上方的电阻元件层的电阻元件的周边区域 通过第一绝缘膜，经由第二绝缘膜设置在电阻元件层的一部分上的虚设层，设置在距虚拟层第一距离的电阻元件层上的第三绝缘膜，设置在第一绝缘膜上的第四绝缘膜 半导体层与电阻元件层隔开第二距离，以及接触第三绝缘膜的接触点，并且连接到电阻元件层，第一距离短于第二距离。

公开(公告)号：US20150035044A1

公开(公告)日：2015-02-05

申请号：US14486421

申请日：2014-09-15

申请人： Spansion LLC

发明人： Tung-Sheng Chen ,  Shenqing Fang

IPC分类号： H01L29/51 ,  H01L29/792 ,  H01L27/115

CPC分类号： H01L29/513 ,  H01L21/3081 ,  H01L21/762 ,  H01L21/76232 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

摘要： A semiconductor processing method to provide a high quality bottom oxide layer and top oxide layer in a charged-trapping NAND and NOR flash memory. Both the bottom oxide layer and the top oxide layer of NAND and NOR flash memory determines array device performance and reliability. The method describes overcomes the corner thinning issue and the poor top oxide quality that results from the traditional oxidation approach of using pre-deposited silicon-rich nitride.

摘要翻译： 一种在充电捕获NAND和NOR闪存中提供高质量底部氧化物层和顶部氧化物层的半导体处理方法。 NAND和NOR闪存的底部氧化物层和顶部氧化物层均决定阵列器件的性能和可靠性。 该方法描述了克服了使用预沉积富硅氮化物的传统氧化方法导致的角部变薄问题和差的顶部氧化物质量。

公开(公告)号：US20150008507A1

公开(公告)日：2015-01-08

申请号：US14320874

申请日：2014-07-01

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Yasufumi MORIMOTO

IPC分类号： H01L27/11 ,  H01L21/28 ,  H01L21/283 ,  H01L27/092

CPC分类号： H01L21/283 ,  H01L27/11573 ,  H01L29/40117

摘要： Provided are a semiconductor device in which a data re-write operation can be performed a larger number of times and a data re-write operation is performed at a higher speed and a manufacturing method thereof. The semiconductor device includes a substrate, a first gate electrode, a second gate electrode, an insulating film, and a pair of source/drain regions. The first gate electrode is formed of a semiconductor layer containing an impurity of a first conductivity type. The second gate electrode is formed of a semiconductor layer containing an impurity of a second conductivity type. Each of the source/drain regions contains an impurity of the first conductivity type. The source region includes a first source region and a second source region having a concentration of the impurity of the first conductivity type higher than that of the first source region.

摘要翻译： 提供一种其中可以执行更多次数据重写操作并且以更高速度执行数据重写操作的半导体器件及其制造方法。 半导体器件包括衬底，第一栅电极，第二栅电极，绝缘膜和一对源/漏区。 第一栅极由包含第一导电类型的杂质的半导体层形成。 第二栅电极由含有第二导电类型的杂质的半导体层形成。 每个源/漏区包含第一导电类型的杂质。 源区包括第一源区和第二源区，其第一导电类型的杂质的浓度高于第一源区。

公开(公告)号：US20140349472A1

公开(公告)日：2014-11-27

申请号：US14455271

申请日：2014-08-08

申请人： National Chiao Tung University

发明人： Albert Chin ,  Chun-Yang Tsai

IPC分类号： H01L29/51 ,  H01L29/49

CPC分类号： H01L29/513 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

摘要： A MONOS Charge-Trapping flash (CTF), with record thinnest 3.6 nm ENT trapping layer, has a large 3.1 V 10-year extrapolated retention window at 125° C. and excellent 106 endurance at a fast 100 μs and ±16 V program/erase. This is achieved using As+-implanted higher κ trapping layer with deep 5.1 eV work-function of As. In contrast, the un-implanted device only has a small 10-year retention window of 1.9 V at 125° C. A MoN—[SiO2—LaAlO3]—[Ge—HfON]—[LaAlO3—SiO2]—Si CTF device is also provided with record-thinnest 2.5-nm Equivalent-Si3N4-Thickness (ENT) trapping layer, large 4.4 V initial memory window, 3.2 V 10-year extrapolated retention window at 125° C., and 3.6 V endurance window at 106 cycles, under very fast 100 μs and low ±16 V program/erase. These were achieved using Ge reaction with HfON trapping layer for better charge-trapping and retention.

摘要翻译： 具有记录最薄的3.6 nm ENT捕获层的MONOS电荷俘获闪光（CTF）在125°C时具有大的3.1 V 10年外推保留窗，在快速100μs和±16 V程序/ 擦除 这是使用As + -implanted higher＆kgr 具有深度5.1 eV功能的陷阱层。 相比之下，未植入的装置在125℃仅具有1.9V的小的10年保留窗口.MN- [SiO 2 -AlAl 3/3] - [Ge-HfON] - [LaAlO 3 -Si 2] -Si CTF装置是 还提供了记录最薄的2.5nm等效Si 3 N 4厚度（ENT）捕获层，大4.4V初始记忆窗口，125℃下3.2V 10年外推保留窗口以及106个周期的3.6V耐久窗口， 在非常快的100μs和低±16 V程序/擦除。 这些是通过与HfON捕获层的Ge反应来实现的，以更好的电荷捕获和保留。

公开(公告)号：US20140332876A1

公开(公告)日：2014-11-13

申请号：US14340054

申请日：2014-07-24

申请人： Spansion LLC

发明人： Shenqing FANG ,  Chun CHEN

IPC分类号： H01L29/423 ,  H01L27/11

CPC分类号： H01L29/42344 ,  H01L27/11 ,  H01L27/11546 ,  H01L27/11563 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/40117 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

摘要： Embodiments described herein generally relate to methods of manufacturing charge-trapping memory by patterning the high voltage gates before other gates are formed. One advantage of such an approach is that a thin poly layer may be used to form memory and low voltage gates while protecting high voltage gates from implant penetration. One approach to accomplishing this is to dispose the layer of poly, and then dispose a mask and a thick resist to pattern the high voltage gates. In this manner, the high voltage gates are formed before either the low voltage gates or the memory cells.

摘要翻译： 本文描述的实施例通常涉及通过在形成其它栅极之前图案化高电压门来制造电荷俘获存储器的方法。 这种方法的一个优点是可以使用薄的多晶硅层来形成存储器和低电压栅极，同时保护高压栅极免受植入物渗透。 实现这一点的一个方法是设置多晶硅层，然后配置掩模和厚的抗蚀剂以对高电压栅极进行图案化。 以这种方式，在低电压门或存储单元之前形成高电压门。

公开(公告)号：US20140327066A1

公开(公告)日：2014-11-06

申请号：US14335401

申请日：2014-07-18

申请人： Renesas Electronics Corporation

发明人： Itaru YANAGI ,  Toshiyuki MINE ,  Hirotaka HAMAMURA ,  Digh HISAMOTO ,  Yasuhiro SHIMAMOTO

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  G11C16/0466 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/513

摘要： In a non-volatile memory in which writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film serving as a charge accumulation layer, in order to realize a high efficiency of a hole injection from a gate electrode, the gate electrode of a memory cell comprises a laminated structure made of a plurality of polysilicon films with different impurity concentrations, for example, a two-layered structure comprising a p-type polysilicon film with a low impurity concentration and a p|-type polysilicon film with a high impurity concentration deposited thereon.

摘要翻译： 在通过将电子和空穴注入到用作电荷累积层的氮化硅膜中来改变总电荷量进行写/擦除的非易失性存储器中，为了实现从栅极的空穴注入的高效率 电极，存储单元的栅电极包括由具有不同杂质浓度的多个多晶硅膜制成的层压结构，例如包括具有低杂质浓度的p型多晶硅膜和具有较低杂质浓度的双层结构的双层结构 沉积有高杂质浓度的多晶硅膜。

公开(公告)号：US20140167142A1

公开(公告)日：2014-06-19

申请号：US13715673

申请日：2012-12-14

申请人： SPANSION LLC

发明人： Chun Chen ,  Mark Ramsbey ,  Shenqing Fang

IPC分类号： H01L29/792 ,  H01L29/66

CPC分类号： H01L27/11568 ,  H01L27/1052 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

摘要： A semiconductor device and method of making such device is presented herein. The method includes disposing a gate layer over a dielectric layer on a substrate and further disposing a cap layer over the gate layer. A first transistor gate is defined having an initial thickness substantially equal to a combined thickness of the cap layer and the gate layer. A first doped region is formed in the substrate adjacent to the first transistor gate. The cap layer is subsequently removed and a second transistor gate is defined having a thickness substantially equal to the thickness of the gate layer. Afterwards, a second doped region is formed in the substrate adjacent to the second transistor gate. The first doped region extends deeper in the substrate than the second doped region, and a final thickness of the first transistor gate is substantially equal to the thickness of the second transistor gate.

摘要翻译： 本文提供了制造这种装置的半导体器件和方法。 该方法包括在衬底上的电介质层上设置栅极层，并且在栅极层上进一步设置覆盖层。 第一晶体管栅极被限定为具有基本上等于盖层和栅极层的组合厚度的初始厚度。 在与第一晶体管栅极相邻的衬底中形成第一掺杂区。 盖层随后被去除，并且限定具有基本上等于栅极层厚度的厚度的第二晶体管栅极。 之后，在与第二晶体管栅极相邻的衬底中形成第二掺杂区。 第一掺杂区域在衬底中比第二掺杂区域更深，并且第一晶体管栅极的最终厚度基本上等于第二晶体管栅极的厚度。

公开(公告)号：US20140134950A1

公开(公告)日：2014-05-15

申请号：US14143385

申请日：2013-12-30

申请人： Glenn J. Leedy

发明人： Glenn J. Leedy

IPC分类号： H04W4/00

CPC分类号： H04W4/80 ,  B81B7/02 ,  B81C1/00238 ,  B81C1/00246 ,  B81C2203/0771 ,  G06F17/5068 ,  H01L21/8252 ,  H01L21/84 ,  H01L22/34 ,  H01L23/481 ,  H01L23/52 ,  H01L23/544 ,  H01L23/66 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10805 ,  H01L27/115 ,  H01L27/118 ,  H01L27/11803 ,  H01L27/1203 ,  H01L27/1463 ,  H01L27/14643 ,  H01L27/14683 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7827 ,  H01L29/7831 ,  H01L29/78648 ,  H01L29/7881 ,  H01L2223/54453 ,  H01L2223/6677 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/00

摘要： The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs.

公开(公告)号：US20140001537A1

公开(公告)日：2014-01-02

申请号：US14019192

申请日：2013-09-05

申请人： Spansion LLC

发明人： Shenqing FANG ,  Angela HUI ,  Shao-Yu TING ,  Inkuk KANG ,  Gang XUE

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L21/76224 ,  H01L27/11568 ,  H01L29/40117

摘要： A method for fabricating a memory device with U-shaped trap layers over rounded active region corners is disclosed. In the present invention, an STI process is performed before the charge-trapping layer is formed. Immediately after the STI process, the sharp corners of the active regions are exposed, making them available for rounding. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, a bottom oxide layer, nitride layer, and sacrificial top oxide layer are formed. An organic bottom antireflective coating applied to the charge trapping layer is planarized. Now the organic bottom antireflective coating, sacrificial top oxide layer, and nitride layer are etched, without etching the sacrificial top oxide layer and nitride layer over the active regions. After the etching the charge trapping layer has a cross-sectional U-shape appearance. U-shaped trap layer edges allow for increased packing density and integration while maintaining isolation between trap layers.

摘要翻译： 公开了一种在圆形有源区域角上制造具有U形陷阱层的存储器件的方法。 在本发明中，在形成电荷俘获层之前进行STI工艺。 在STI处理之后，活动区域的尖角暴露，使其可用于四舍五入。 四舍五入改善了存储设备的性能特征。 在舍入处理之后，形成底部氧化物层，氮化物层和牺牲顶部氧化物层。 施加到电荷捕获层的有机底部抗反射涂层被平坦化。 现在蚀刻有机底部抗反射涂层，牺牲顶部氧化物层和氮化物层，而不在有源区域上蚀刻牺牲顶部氧化物层和氮化物层。 在蚀刻之后，电荷捕获层具有横截面的U形外观。 U形陷阱层边缘允许增加堆积密度和集成度，同时保持捕集层之间的隔离。